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Socrates D. Vamvakos, Ph.D. - Publications

Affiliations: 
2005 University of California, Berkeley, Berkeley, CA, United States 
Area:
Integrated Circuits (INC); Communications & Networking (COMNET); Design, Modeling and Analysis (DMA); Computer Architecture & Engineering (ARC)
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11 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Vamvakos SD, Boecker C, Groen E, Wang A, Desai S, Irwin S, Rao V, Bottelli A, Chen J, Chen X, Choudhary P, Hsieh KC, Jennings P, Lin H, Pechiu D, et al. A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop Proceedings of the Ieee 2014 Custom Integrated Circuits Conference, Cicc 2014. DOI: 10.1109/CICC.2014.6945979  0.325
2014 Vamvakos SD, Gauthier CR, Rao C, Wang A, Canagasaby KR, Abugharbieh K, Choudhary P, Dabral S, Desai S, Hassan M, Hsieh KC, Kleveland B, Mandal G, Rouse R, Saraf R, et al. A 2.488-11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications Analog Integrated Circuits and Signal Processing. 78: 259-273. DOI: 10.1007/S10470-013-0172-1  0.341
2011 Waheed K, Staszewski RB, Dülger F, Ullah MS, Vamvakos SD. Spurious-free time-to-digital conversion in an ADPLL using short dithering sequences Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 2051-2060. DOI: 10.1109/Tcsi.2011.2163981  0.452
2011 Vamvakos SD, Stojanović V, Nikolić B. Discrete-time, linear periodically time-variant phase-locked loop model for jitter analysis Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 1211-1224. DOI: 10.1109/Tcsi.2010.2097694  0.341
2009 Vamvakos SD, Zhuang J, Waheed K. Computationally efficient, event-driven simulation of wireless transmitters using a noisy local oscillator Proceedings of the 2009 Ieee Dallas Circuits and Systems Workshop: Energy Efficient Circuits and Systems, Dcas-2009. 48-51. DOI: 10.1109/DCAS.2009.5505722  0.325
2009 Vamvakos SD, Stojanović V, Nikolić B. Discrete-time, cyclostationary phase-locked loop model for jitter analysis Proceedings of the Custom Integrated Circuits Conference. 637-640. DOI: 10.1109/CICC.2009.5280745  0.609
2006 Vamvakos SD, Staszewski RB, Sheba M, Waheed K. Noise analysis of time-to-digital converter in all-digital PLLs 2006 Ieee Dallas/Cas Workshop Ondesign, Applications, Integration and Software, Dcas-06. 87-90. DOI: 10.1109/DCAS.2006.321040  0.346
2004 Vamvakos SD, Werner C, Nikolić B. Phase-locked loop architecture for adaptive jitter optimization Proceedings - Ieee International Symposium On Circuits and Systems. 4: IV-161-IV-164.  0.341
1998 Vamvakos S, Anantharam V. Queueing Systems. 28: 191-214. DOI: 10.1023/A:1019155307901  0.338
1998 Vamvakos S, Anantharam V. On the departure process of a leaky bucket system with long-range dependent input traffic Queueing Systems. 28: 191-214.  0.318
1995 Mitrou N, Vamvakos S, Kontovasilis K. Modelling, parameter assessment and multiplexing analysis of bursty sources with hyper-exponentially distributed bursts Computer Networks and Isdn Systems. 27: 1175-1192. DOI: 10.1016/0169-7552(94)00014-K  0.362
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