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Sourindra M. Chaudhuri, Ph.D. - Publications

Affiliations: 
2015 Electrical Engineering Princeton University, Princeton, NJ 
Area:
Biological & Biomedical,Computing & Networking,Energy & Environment,High-Performance Computing,Integrated Electronic Systems,Nanotechnologies,Quantum Information,Security
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6 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2016 Chaudhuri SM, Jha NK. Ultra-low-leakage and high-performance logic circuit design using multiparameter asymmetric FinFETs Acm Journal On Emerging Technologies in Computing Systems. 12. DOI: 10.1145/2832913  0.529
2016 Chaudhuri S, Bhoj AN, Bhattacharya D, Jha NK. Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism Proceedings of the Ieee International Conference On Vlsi Design. 2016: 300-305. DOI: 10.1109/VLSID.2016.34  0.306
2014 Chaudhuri SM, Mishra P, Jha NK. Accurate leakage/delay estimation for FinFET standard cells under PVT variations using the response surface methodology Acm Journal On Emerging Technologies in Computing Systems. 11. DOI: 10.1145/2665066  0.649
2014 Chaudhuri SM, Jha NK. 3D vs. 2D device simulation of FinFET logic gates under PVT variations Acm Journal On Emerging Technologies in Computing Systems. 10. DOI: 10.1145/2567670  0.685
2012 Chaudhuri S, Mishra P, Jha NK. Accurate leakage estimation for FinFET standard cells using the response surface methodology Proceedings of the Ieee International Conference On Vlsi Design. 238-244. DOI: 10.1109/VLSID.2012.77  0.615
2011 Chaudhuri S, Jha NK. 3D vs. 2D analysis of FinFET logic gates under process variations Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 435-436. DOI: 10.1109/ICCD.2011.6081437  0.603
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