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Nagarajan Ranganathan - Publications

Affiliations: 
University of South Florida, Tampa, FL, United States 
Area:
Electronics and Electrical Engineering, Computer Science
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88 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2018 Aditham S, Ranganathan N. A System Architecture for the Detection of Insider Attacks in Big Data Systems Ieee Transactions On Dependable and Secure Computing. 15: 974-987. DOI: 10.1109/Tdsc.2017.2768533  0.728
2015 Morrison MA, Ranganathan N, Ligatti J. Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 1381-1389. DOI: 10.1109/Tvlsi.2014.2342034  0.663
2015 Kotiyal S, Thapliyal H, Ranganathan N. Reversible logic based multiplication computing unit using binary tree data structure Journal of Supercomputing. DOI: 10.1007/S11227-015-1410-3  0.8
2015 Casagrande T, Ranganathan N. GTFUZZ: A novel algorithm for robust dynamic power optimization via gate sizing with fuzzy games Proceedings -Design, Automation and Test in Europe, Date. 2015: 677-682.  0.328
2014 Morrison M, Ranganathan N. Forward body biased adiabatic logic for peak and average power reduction in 22nm CMOS Proceedings of the Ieee International Conference On Vlsi Design. 470-475. DOI: 10.1109/VLSID.2014.88  0.3
2014 Morrison M, Ranganathan N. Synthesis of dual-rail adiabatic logic for low power security applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 975-988. DOI: 10.1109/Tcad.2014.2313454  0.699
2014 Kotiyal S, Thapliyal H, Ranganathan N. Efficient reversible NOR gates and their mapping in optical computing domain Microelectronics Journal. 45: 825-834. DOI: 10.1016/J.Mejo.2014.03.001  0.767
2013 Thapliyal H, Ranganathan N. Design of efficient reversible logic-based binary and BCD adder circuits Acm Journal On Emerging Technologies in Computing Systems. 9. DOI: 10.1145/2491682  0.686
2013 Hyman R, Ranganathan N, Bingel T, Vo DT. A clock control strategy for peak power and RMS current reduction using path clustering Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 259-269. DOI: 10.1109/Tvlsi.2012.2186989  0.451
2013 Morrison M, Ranganathan N. A novel optimization method for reversible logic circuit minimization Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 182-187. DOI: 10.1109/ISVLSI.2013.6654656  0.326
2013 Kundu S, Mohanty SP, Ranganathan N. Design methodologies for nanoelectronic digital and analogue circuits Iet Circuits, Devices and Systems. 7: 221-222. DOI: 10.1049/Iet-Cds.2013.0269  0.557
2012 Mahalingam V, Ranganathan N, Hyman R. Dynamic clock stretching for variation compensation in VLSI circuit design Acm Journal On Emerging Technologies in Computing Systems. 8. DOI: 10.1145/2287696.2287699  0.634
2012 Thapliyal H, Ranganathan N. Design, synthesis and test of reversible circuits for emerging nanotechnologies Proceedings - 2012 Ieee Computer Society Annual Symposium On Vlsi, Isvlsi 2012. 5-6. DOI: 10.1109/ISVLSI.2012.83  0.648
2011 Gupta U, Ranganathan N. A utilitarian approach to variation aware delay, power, and crosstalk noise optimization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1723-1726. DOI: 10.1109/Tvlsi.2010.2053394  0.452
2011 Bhattacharya K, Ranganathan N. Placement for immunity of transient faults in cell-based design of nanometer circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 918-923. DOI: 10.1109/Tvlsi.2010.2040295  0.735
2011 Roy S, Ranganathan N, Katkoori S. State-retentive power gating of register files in multicore processors featuring multithreaded in-order cores Ieee Transactions On Computers. 60: 1547-1560. DOI: 10.1109/Tc.2010.249  0.704
2011 Hyman R, Bhattacharya K, Ranganathan N. Redundancy mining for soft error detection in multicore processors Ieee Transactions On Computers. 60: 1114-1125. DOI: 10.1109/Tc.2010.168  0.757
2011 Thapliyal H, Ranganathan N. A new design of the reversible subtractor circuit Proceedings of the Ieee Conference On Nanotechnology. 1430-1435. DOI: 10.1109/NANO.2011.6144350  0.618
2011 Thapliyal H, Ranganathan N. A new reversible design of BCD adder Proceedings -Design, Automation and Test in Europe, Date. 1180-1183.  0.625
2010 Thapliyal H, Ranganathan N. Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs Acm Journal On Emerging Technologies in Computing Systems. 6. DOI: 10.1145/1877745.1877748  0.646
2010 Thapliyal H, Ranganathan N. Design of reversible latches optimized for quantum cost, delay and garbage outputs Proceedings of the Ieee International Conference On Vlsi Design. 235-240. DOI: 10.1109/VLSI.Design.2010.74  0.613
2010 Mahalingam V, Bhattacharya K, Ranganathan N, Chakravarthula H, Murphy RR, Pratt KS. A VLSI architecture and algorithm for Lucas-Kanade-based optical flow computation Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 18: 29-38. DOI: 10.1109/Tvlsi.2008.2006900  0.713
2010 Thapliyal H, Ranganathan N. Reversible logic-based concurrently testable latches for molecular QCA Ieee Transactions On Nanotechnology. 9: 62-69. DOI: 10.1109/Tnano.2009.2025038  0.621
2010 Gupta U, Ranganathan N. A game theoretic approach for simultaneous compaction and equipartitioning of spatial data sets Ieee Transactions On Knowledge and Data Engineering. 22: 465-478. DOI: 10.1109/TKDE.2009.110  0.506
2010 Thapliyal H, Ranganathan N. Reversible logic based concurrent error detection methodology for emerging nanocircuits 2010 10th Ieee Conference On Nanotechnology, Nano 2010. 217-222. DOI: 10.1109/NANO.2010.5697743  0.629
2009 Ranganathan N, Gupta U, Mahalingam V. Variation-aware multimetric optimization during gate sizing Acm Transactions On Design Automation of Electronic Systems. 14. DOI: 10.1145/1562514.1562522  0.565
2009 Bhattacharya K, Ranganathan N. RADJAM: A novel approach for reduction of soft errors in logic circuits Proceedings: 22nd International Conference On Vlsi Design - Held Jointly With 7th International Conference On Embedded Systems. 453-458. DOI: 10.1109/VLSI.Design.2009.76  0.35
2009 Thapliyal H, Ranganathan N. Conservative QCA gate (CQCA) for designing concurrently testable molecular QCA circuits Proceedings: 22nd International Conference On Vlsi Design - Held Jointly With 7th International Conference On Embedded Systems. 511-516. DOI: 10.1109/VLSI.Design.2009.75  0.637
2009 Roy S, Ranganathan N, Katkoori S. A framework for power-gating functional units in embedded microprocessors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1640-1649. DOI: 10.1109/Tvlsi.2008.2005774  0.709
2009 Thapliyal H, Ranganathan N. Design of efficient reversible binary subtractors based on a new reversible gate Proceedings of the 2009 Ieee Computer Society Annual Symposium On Vlsi, Isvlsi 2009. 229-234. DOI: 10.1109/ISVLSI.2009.49  0.63
2009 Bhattacharya K, Ranganathan N. A new placement algorithm for reduction of soft errors in macrocell based design of nanometer circuits Proceedings of the 2009 Ieee Computer Society Annual Symposium On Vlsi, Isvlsi 2009. 91-96. DOI: 10.1109/ISVLSI.2009.37  0.335
2009 Thapliyal H, Ranganathan N. Concurrently testable FPGA design for molecular QCA using conservative reversible logic gate Proceedings - Ieee International Symposium On Circuits and Systems. 1815-1818. DOI: 10.1109/ISCAS.2009.5118130  0.625
2008 Bhattacharya K, Ranganathan N. Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power Proceedings of the International Symposium On Low Power Electronics and Design. 99-104. DOI: 10.1145/1393921.1393948  0.337
2008 Gupta U, Ranganathan N. An expected-utility based approach to variation aware VLSI optimization under scarce information Proceedings of the International Symposium On Low Power Electronics and Design. 81-86. DOI: 10.1145/1393921.1393945  0.542
2008 Bhattacharya K, Ranganathan N. A linear programming formulation for security-aware gate sizing Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 273-278. DOI: 10.1145/1366110.1366176  0.372
2008 Thapliyal H, Ranganathan N. Testable reversible latches for molecular QCA 2008 8th Ieee Conference On Nanotechnology, Ieee-Nano. 699-702. DOI: 10.1109/NANO.2008.211  0.621
2008 Gupta U, Ranganathan N. A microeconomic approach to multi-objective spatial clustering Proceedings - International Conference On Pattern Recognition.  0.467
2007 Ranganathan N, Gupta U, Shetty R, Murugavel A. An Automated Decision Support System Based on Game Theoretic Optimization for Emergency Management in Urban Environments Journal of Homeland Security and Emergency Management. 4. DOI: 10.2202/1547-7355.1236  0.475
2007 Gupta U, Ranganathan N. Multievent crisis management using noncooperative multistep games Ieee Transactions On Computers. 56: 577-589. DOI: 10.1109/Tc.2007.1023  0.533
2007 Hanchate N, Ranganathan N. Statistical gate sizing for yield enhancement at post layout level Proceedings - Ieee Computer Society Annual Symposium On Vlsi: Emerging Vlsi Technologies and Architectures. 245-250. DOI: 10.1109/ISVLSI.2007.92  0.773
2007 Hanchate N, Ranganathan N. Integrated gate and wire sizing at post layout level Proceedings - Ieee Computer Society Annual Symposium On Vlsi: Emerging Vlsi Technologies and Architectures. 225-230. DOI: 10.1109/ISVLSI.2007.59  0.769
2007 Mohanty SP, Kougianos E, Ranganathan N. VLSI architecture and chip for combined invisible robust and fragile watermarking Iet Computers and Digital Techniques. 1: 600-611. DOI: 10.1049/Iet-Cdt:20070057  0.573
2006 Hanchate N, Ranganathan N. A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing Acm Transactions On Design Automation of Electronic Systems. 11: 711-739. DOI: 10.1145/1142980.1142988  0.782
2006 Mohanty SP, Ranganathan N, Chappidi SK. ILP models for simultaneous energy and transient power minimization during behavioral synthesis Acm Transactions On Design Automation of Electronic Systems. 11: 186-212. DOI: 10.1145/1124713.1124725  0.558
2006 Sairaman V, Ranganathan N, Singh NS. An automatic code generation tool for partitioned software in distributed systems Proceedings of the Ieee International Conference On Vlsi Design. 2006: 477-480. DOI: 10.1109/VLSID.2006.41  0.727
2006 Hanchate N, Ranganathan N. A linear time algorithm for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise Proceedings of the Ieee International Conference On Vlsi Design. 2006: 283-290. DOI: 10.1109/VLSID.2006.11  0.782
2006 Mohanty SP, Ranganathan N, Balakrishnan K. A dual voltage-frequency VLSI chip for image watermarking in DCT domain Ieee Transactions On Circuits and Systems Ii: Express Briefs. 53: 394-398. DOI: 10.1109/Tcsii.2006.870216  0.575
2006 Mahalingam V, Ranganathan N. Improving accuracy in Mitchell's logarithmic multiplication using operand decomposition Ieee Transactions On Computers. 55: 1523-1535. DOI: 10.1109/Tc.2006.198  0.379
2006 Hanchate N, Ranganathan N. Simultaneous interconnect delay and crosstalk noise optimization through gate sizing using game theory Ieee Transactions On Computers. 55: 1011-1023. DOI: 10.1109/Tc.2006.131  0.782
2006 Hanchate N, Ranganathan N. Post-layout gate sizing for interconnect delay and crosstalk noise optimization Proceedings - International Symposium On Quality Electronic Design, Isqed. 92-97. DOI: 10.1109/ISQED.2006.101  0.761
2005 Mohanty SP, Ranganathan N. Energy-efficient datapath scheduling using multiple voltages and dynamic clocking Acm Transactions On Design Automation of Electronic Systems. 10: 330-353. DOI: 10.1145/1059876.1059883  0.556
2005 Mohanty SP, Ranganathan N, Namballa RK. A VLSI architecture for visible watermarking in a secure still digital camera (S 2DC) design (corrected) Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1002-1011. DOI: 10.1109/Tvlsi.2005.857991  0.552
2005 Mohanty SP, Ranganathan N, Namballa RK. A VLSI architecture for watermarking in a secure still digital camera (S 2DC) design Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 808-817. DOI: 10.1109/Tvlsi.2005.850095  0.552
2005 Mohanty SP, Ranganathan N. Simultaneous peak and average power minimization during datapath scheduling Ieee Transactions On Circuits and Systems I: Regular Papers. 52: 1157-1165. DOI: 10.1109/Tcsi.2005.849131  0.572
2004 Bhanja S, Ranganathan N. Cascaded Bayesian inferencing for switching activity estimation with correlated inputs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 1360-1370. DOI: 10.1109/Tvlsi.2004.837991  0.608
2004 Mohanty SP, Ranganathan N. A framework for energy and transient power reduction during behavioral synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 562-572. DOI: 10.1109/Tvlsi.2004.827568  0.491
2004 Hanchate N, Ranganathan N. LECTOR: A Technique for Leakage Reduction in CMOS Circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 196-205. DOI: 10.1109/TVLSI.2003.821547  0.758
2004 Hanchate N, Ranganathan N. A new technique for leakage reduction in CMOS circuits using self-controlled stacked transistors Proceedings of the Ieee International Conference On Vlsi Design. 17: 228-233.  0.749
2004 Murugavel AK, Ranganathan N. Game theoretic modeling of voltage and frequency scaling during behavioral synthesis Proceedings of the Ieee International Conference On Vlsi Design. 17: 670-673.  0.797
2004 Murugavel AK, Ranganathan N. Gate sizing and buffer insertion using economic models for power optimization Proceedings of the Ieee International Conference On Vlsi Design. 17: 195-200.  0.816
2003 Ranganathan N, Murugavel AK. A Low Power Scheduler Using Game Theory Hardware/Software Codesign - Proceedings of the International Workshop. 126-131. DOI: 10.1145/944678.944681  0.8
2003 Murugavel AK, Ranganathan N. A game theoretic approach for power optimization during behavioral synthesis Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 1031-1043. DOI: 10.1109/Tvlsi.2003.819566  0.805
2003 Bhanja S, Ranganathan N. Switching Activity Estimation of VLSI Circuits Using Bayesian Networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 558-567. DOI: 10.1109/Tvlsi.2003.816144  0.63
2003 Murugavel AK, Ranganathan N. A game-theoretic approach for binding in behavioral synthesis Proceedings of the Ieee International Conference On Vlsi Design. 2003: 452-458. DOI: 10.1109/ICVD.2003.1183176  0.801
2003 Mohanty SP, Ranganathan N. Energy efficient scheduling for datapath synthesis Proceedings of the Ieee International Conference On Vlsi Design. 2003: 446-451. DOI: 10.1109/ICVD.2003.1183175  0.482
2003 Ranganathan N, Murugavel AK. A microeconomic model for simultaneous gate sizing and voltage scaling for power optimization Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 276-281.  0.814
2002 Murugavel AK, Ranganathan N. Petri net modeling of gate and interconnect delays for power estimation Proceedings - Design Automation Conference. 455-460. DOI: 10.1109/TVLSI.2003.817110  0.804
2002 Murugavel AK, Ranganathan N. Petri net modeling of gate and interconnect delays for power estimation Proceedings - Design Automation Conference. 455-460. DOI: 10.1109/Tvlsi.2003.817110  0.804
2002 Bhanja S, Ranganathan N. Switching activity estimation of large circuits using multiple Bayesian networks Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference On Vlsi Design, Asp-Dac/Vlsi Design 2002. 187-192. DOI: 10.1109/ASPDAC.2002.994917  0.574
2002 Murugavel AK, Ranganathan N. A real delay switching activity simulator based on Petri net modeling Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference On Vlsi Design, Asp-Dac/Vlsi Design 2002. 181-186. DOI: 10.1109/ASPDAC.2002.994915  0.802
2002 Murugavel AK, Ranganathan N, Chandramouli R, Chavali S. Least-square estimation of average power in digital CMOS circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 10: 55-58. DOI: 10.1109/92.988730  0.797
2002 Oi H, Ranganathan N. A comparative study of bidirectional ring and crossbar interconnection networks Computers and Electrical Engineering. 28: 43-57. DOI: 10.1016/S0045-7906(00)00044-6  0.588
2002 Bhanja S, Ranganathan N. Modeling switching activity using Cascaded Bayesian Networks for correlated input streams Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 388-390.  0.546
2002 Murugavel AK, Ranganathan N. Power estimation of sequential circuits using hierarchical colored hardware Petri net modeling Proceedings of the International Symposium On Low Power Electronics and Design, Digest of Technical Papers. 267-270.  0.804
2001 Ejnioui A, Ranganathan N. A partitioning algorithm for technology-mapped designs on single-chip emulation systems Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 9: 407-410. DOI: 10.1109/92.924064  0.307
2001 Bhanja S, Ranganathan N. Dependency preserving probabilistic modeling of switching activity using Bayesian Networks Proceedings - Design Automation Conference. 209-214.  0.558
2000 Oi H, Ranganathan N. Utilization of cache area in on-chip multiprocessor Microprocessors and Microsystems. 24: 429-436. DOI: 10.1016/S0141-9331(00)00094-6  0.574
1999 Ejnioui A, Ranganathan N. Multi-terminal net routing for partial crossbar-based multi-FPGA systems Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 176-184. DOI: 10.1109/Tvlsi.2002.800523  0.369
1999 Krishna V, Chandramouli R, Ranganathan N. Computation of lower bounds for switching activity using decision theory Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 7: 125-129. DOI: 10.1109/92.748209  0.384
1998 Krishna V, Ranganathan N. Methodology for high level power estimation and exploration Proceedings of the Ieee Great Lakes Symposium On Vlsi. 420-425. DOI: 10.1109/GLSV.1998.665337  0.33
1998 Sastry R, Ranganathan N. A VLSI architecture for approximate tree matching Ieee Transactions On Computers. 47: 346-352. DOI: 10.1109/12.660171  0.68
1995 Ranganathan N, Romaniuk SG, Rao Namuduri K. A lossless image compression algorithm using variable block size segmentation. Ieee Transactions On Image Processing : a Publication of the Ieee Signal Processing Society. 4: 1396-406. PMID 18291971 DOI: 10.1109/83.465104  0.32
1992 Nichani S, Ranganathan N. Design of a systolic VLSI chip for computing scale space Proceedings of Spie - the International Society For Optical Engineering. 1708: 146-156. DOI: 10.1117/12.58568  0.387
1991 Mukherjee A, Ranganathan N, Bassiouni M. Efficient VLSI Designs for Data Transformation of Tree-Based Codes Ieee Transactions On Circuits and Systems. 38: 306-314. DOI: 10.1109/31.101323  0.538
1991 Ranganathan N, Srinidhi HN. A suggestion for performance improvement in a relational database machine Computers and Electrical Engineering. 17: 245-259. DOI: 10.1016/0045-7906(91)90010-W  0.311
1989 Bassiouni MA, Mukherjee A, Ranganathan N. Enhancing arithmetic and tree-based coding Information Processing and Management. 25: 293-305. DOI: 10.1016/0306-4573(89)90046-0  0.684
1989 Bassiouni MA, Mukherjee A, Ranganathan N. On software and hardware techniques of data engineering . 208-215.  0.614
1988 Bassiouni MA, Ranganathan N, Mukherjee A. Scheme for data compression in supercomputers . 272-278.  0.604
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