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Moongon Jung - Publications

Affiliations: 
2014 Georgia Institute of Technology, Atlanta, GA 
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6 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Ceyhan A, Jung M, Panth S, Lim SK, Naeemi A. Evaluating Chip-Level Impact of Cu/Low-κ Performance Degradation on Circuit Performance at Future Technology Nodes Ieee Transactions On Electron Devices. DOI: 10.1109/Ted.2015.2394407  0.675
2015 Jung M, Song T, Peng Y, Lim SK. Fine-Grained 3-D IC Partitioning Study With a Multicore Processor Ieee Transactions On Components, Packaging and Manufacturing Technology. DOI: 10.1109/Tcpmt.2015.2470124  0.628
2015 Kim DH, Athikulwongse K, Healy MB, Hossain MM, Jung M, Khorosh I, Kumar G, Lee YJ, Lewis DL, Lin TW, Liu C, Panth S, Pathak M, Ren M, Shen G, et al. Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory) Ieee Transactions On Computers. 64: 112-125. DOI: 10.1109/Tc.2013.192  0.402
2014 Jung M, Mitra J, Pan DZ, Lim SK. TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC Communications of the Acm. 57: 107-115. DOI: 10.1145/2494536  0.507
2013 Jung M, Pan DZ, Lim SK. Chip/Package Mechanical Stress Impact on 3-D IC Reliability and Mobility Variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1694-1707. DOI: 10.1109/Tcad.2013.2265372  0.433
2012 Jung M, Mitra J, Pan DZ, Lim SK. TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1194-1207. DOI: 10.1109/Tcad.2012.2188400  0.412
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