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Krishnendu Chakrabarty - Publications

Affiliations: 
1995-1998 Electrical and Computer Engineering Boston University, Boston, MA, United States 
 1998-2022 Electrical and Computer Engineering Duke University, Durham, NC 
 2022- Semiconductor Microelectronics Arizona State University, Tempe, AZ, United States 
Area:
Electronic design automation, Testing and Design-for-Testability, Microfluidics, Computer Engineering, Sensor Networks
Website:
https://search.asu.edu/profile/4669916
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263 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2020 Zhong Z, Zhu H, Zhang P, Morizio J, Huang TJ, Chakrabarty K. Hardware Design and Fault-Tolerant Synthesis for Digital Acoustofluidic Biochips. Ieee Transactions On Biomedical Circuits and Systems. PMID 32816679 DOI: 10.1109/Tbcas.2020.3018136  0.379
2020 Bhattacharjee S, Tang J, Poddar S, Ibrahim M, Karri R, Chakrabarty K. Bio-chemical Assay Locking to Thwart Bio-IP Theft Acm Transactions On Design Automation of Electronic Systems. 25: 1-20. DOI: 10.1145/3365579  0.321
2020 Pan R, Zhang Z, Li X, Chakrabarty K, Gu X. Black-Box Test-Cost Reduction Based on Bayesian Network Models Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.2994257  0.709
2020 Zhong Z, Chakrabarty K. IJTAG-based Fault Recovery and Robust Microelectrode-Cell Design for MEDA Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.2986741  0.321
2020 Shayan M, Liang T, Bhattacharjee S, Chakrabarty K, Karri R. Towards Secure Checkpointing for Micro-Electrode-Dot-Array Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2020.2979972  0.321
2020 Liu C, Li B, Bhattacharya BB, Chakrabarty K, Ho T, Schlichtmann U. Test Generation for Flow-Based Microfluidic Biochips With General Architectures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 2530-2543. DOI: 10.1109/Tcad.2019.2948904  0.35
2020 Koneru A, Chakrabarty K. An Inter-Layer Interconnect BIST and Diagnosis Solution for Monolithic 3D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 1-1. DOI: 10.1109/Tcad.2019.2935410  0.43
2020 Jin S, Zhang Z, Chakrabarty K, Gu X. Self-Learning and Efficient Health-Status Analysis for a Core Router System Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1935-1948. DOI: 10.1109/Tcad.2019.2926506  0.697
2020 Huang X, Ho T, Chakrabarty K, Guo W. Timing-Driven Flow-Channel Network Construction for Continuous-Flow Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1314-1327. DOI: 10.1109/Tcad.2019.2912936  0.328
2020 Tang J, Ibrahim M, Chakrabarty K, Karri R. Analysis and Design of Tamper-Mitigating Microfluidic Routing Fabrics Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 1003-1016. DOI: 10.1109/Tcad.2019.2907881  0.334
2020 Zhang Y, Chakrabarty K, Peng Z, Rezine A, Li H, Eles P, Jiang J. Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 714-727. DOI: 10.1109/Tcad.2018.2890695  0.46
2020 Jin S, Zhang Z, Chakrabarty K, Gu X. Hierarchical Symbol-Based Health-Status Analysis Using Time-Series Data in a Core Router System Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 700-713. DOI: 10.1109/Tcad.2018.2890681  0.698
2020 Moradi Y, Ibrahim M, Chakrabarty K, Schlichtmann U. An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Droplet Barcoding in Single-Cell Analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 359-372. DOI: 10.1109/Tcad.2018.2889765  0.361
2020 Chaudhuri A, Banerjee S, Park H, Kim J, Murali G, Lee E, Kim D, Lim SK, Mukhopadhyay S, Chakrabarty K. Advances in Design and Test of Monolithic 3-D ICs Ieee Design & Test of Computers. 37: 92-100. DOI: 10.1109/Mdat.2020.2988657  0.403
2019 Sridhar A, Ibrahim M, Chakrabarty K. Synterface Acm Transactions On Embedded Computing Systems. 18: 1-21. DOI: 10.1145/3358188  0.324
2019 Lee D, Das S, Doppa JR, Pande PP, Chakrabarty K. Impact of Electrostatic Coupling on Monolithic 3D-enabled Network on Chip Acm Transactions On Design Automation of Electronic Systems. 24: 62. DOI: 10.1145/3357158  0.328
2019 Basu K, Saeed SM, Pilato C, Ashraf M, Nabeel MT, Chakrabarty K, Karri R. CAD-Base Acm Transactions On Design Automation of Electronic Systems. 24: 1-30. DOI: 10.1145/3315574  0.32
2019 Elnaggar R, Chakrabarty K, Tahoori MB. Hardware Trojan Detection Using Changepoint-Based Anomaly Detection Techniques Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 2706-2719. DOI: 10.1109/Tvlsi.2019.2925807  0.335
2019 Shayan M, Bhattacharjee S, Song Y, Chakrabarty K, Karri R. Toward Secure Microfluidic Fully Programmable Valve Array Biochips Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 2755-2766. DOI: 10.1109/Tvlsi.2019.2924915  0.321
2019 Shayan M, Bhattacharjee S, Tang J, Chakrabarty K, Karri R. Bio-Protocol Watermarking on Digital Microfluidic Biochips Ieee Transactions On Information Forensics and Security. 14: 2901-2915. DOI: 10.1109/Tifs.2019.2907185  0.309
2019 Pradhan M, Bhattacharya BB, Chakrabarty K, Bhattacharya BB. Predicting ${X}$ -Sensitivity of Circuit-Inputs on Test-Coverage: A Machine-Learning Approach Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 2343-2356. DOI: 10.1109/Tcad.2018.2878169  0.362
2019 Wang S, Chakrabarty K, Tahoori MB. Defect Clustering-Aware Spare-TSV Allocation in 3-D ICs for Yield Enhancement Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1928-1941. DOI: 10.1109/Tcad.2018.2864291  0.362
2019 Koneru A, Kannan S, Chakrabarty K. A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1942-1955. DOI: 10.1109/Tcad.2018.2864290  0.457
2019 Xia L, Liu M, Ning X, Chakrabarty K, Wang Y. Fault-Tolerant Training Enabled by On-Line Fault Detection for RRAM-Based Neural Computing Systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1611-1624. DOI: 10.1109/Tcad.2018.2855145  0.328
2019 Jin S, Zhang Z, Chakrabarty K, Gu X. Changepoint-Based Anomaly Detection for Prognostic Diagnosis in a Core Router System Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1331-1344. DOI: 10.1109/Tcad.2018.2846641  0.703
2019 Bhattacharjee S, Banerjee A, Ho T, Chakrabarty K, Bhattacharya BB. Efficient Generation of Dilution Gradients With Digital Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 874-887. DOI: 10.1109/Tcad.2018.2834413  0.355
2019 Poddar S, Bhattacharjee S, Nandy SC, Chakrabarty K, Bhattacharya BB. Optimization of Multi-Target Sample Preparation On-Demand With Digital Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 253-266. DOI: 10.1109/Tcad.2018.2808234  0.308
2019 Jin S, Zhang Z, Chakrabarty K, Gu X. Anomaly Detection and Health-Status Analysis in a Core Router System Ieee Design & Test. 36: 7-17. DOI: 10.1109/Mdat.2019.2906108  0.689
2018 Zhong Z, Li Z, Chakrabarty K, Ho TY, Lee CY. Micro-Electrode-Dot-Array Digital Microfluidic Biochips: Technology, Design Automation, and Test Techniques. Ieee Transactions On Biomedical Circuits and Systems. PMID 30571645 DOI: 10.1109/Tbcas.2018.2886952  0.37
2018 Lee D, Das S, Doppa JR, Pande PP, Chakrabarty K. Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip Acm Transactions On Design Automation of Electronic Systems. 23: 1-25. DOI: 10.1145/3223046  0.376
2018 Shalu, Kumar S, Singla A, Roy S, Chakrabarty K, Chakrabarti PP, Bhattacharya BB. Demand-Driven Single- and Multitarget Mixture Preparation Using Digital Microfluidic Biochips Acm Transactions On Design Automation of Electronic Systems. 23: 55. DOI: 10.1145/3200903  0.308
2018 Wang S, Wang R, Chakrabarty K, Tahoori MB. Multicast Testing of Interposer-Based 2.5D ICs Acm Transactions On Design Automation of Electronic Systems. 23: 1-25. DOI: 10.1145/3177879  0.494
2018 Firouzi F, Farahani B, Ibrahim M, Chakrabarty K. Keynote Paper: From EDA to IoT eHealth: Promises, Challenges, and Solutions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2965-2978. DOI: 10.1109/Tcad.2018.2801227  0.314
2018 Georgiou P, Vartziotis F, Kavousianos X, Chakrabarty K. Testing 3D-SoCs Using 2-D Time-Division Multiplexing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 3177-3185. DOI: 10.1109/Tcad.2017.2780054  0.455
2018 Vijayan A, Kiamehr S, Oboril F, Chakrabarty K, Tahoori MB. Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2098-2110. DOI: 10.1109/Tcad.2017.2778254  0.33
2018 Jin S, Zhang Z, Chakrabarty K, Gu X. Toward Predictive Fault Tolerance in a Core-Router System: Anomaly Detection Using Correlation-Based Time-Series Analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 2111-2124. DOI: 10.1109/Tcad.2017.2775240  0.719
2018 Tang J, Ibrahim M, Chakrabarty K, Karri R. Secure Randomized Checkpointing for Digital Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1119-1132. DOI: 10.1109/Tcad.2017.2748030  0.327
2018 Li Z, Lai KY, Yu P, Chakrabarty K, Ho T, Lee C. Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 968-981. DOI: 10.1109/Tcad.2017.2740299  0.414
2018 Tenentes V, Rossi D, Khursheed S, Al-Hashimi BM, Chakrabarty K. Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 883-895. DOI: 10.1109/Tcad.2017.2729462  0.352
2018 Li Z, Lai KY, McCrone J, Yu P, Chakrabarty K, Pajic M, Ho T, Lee C. Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 601-614. DOI: 10.1109/Tcad.2017.2729347  0.329
2018 Vijayan A, Kiamehr S, Ebrahimi M, Chakrabarty K, Tahoori MB. Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic Cores Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 499-511. DOI: 10.1109/Tcad.2017.2706558  0.332
2018 Vijayan A, Koneru A, Kiamehr S, Chakrabarty K, Tahoori MB. Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1064-1075. DOI: 10.1109/Tcad.2016.2620903  0.342
2018 Xia L, Huangfu W, Tang T, Yin X, Chakrabarty K, Xie Y, Wang Y, Yang H. Stuck-at Fault Tolerance in RRAM Computing Systems Ieee Journal On Emerging and Selected Topics in Circuits and Systems. 8: 102-115. DOI: 10.1109/Jetcas.2017.2776980  0.355
2017 Li Z, Lai KY, Yu PH, Chakrabarty K, Ho TY, Lee CY. Droplet Size-Aware High-Level Synthesis for Micro-Electrode-Dot-Array Digital Microfluidic Biochips. Ieee Transactions On Biomedical Circuits and Systems. PMID 28333641 DOI: 10.1109/Tbcas.2017.2653808  0.319
2017 Das S, Lee D, Choi W, Doppa JR, Pande PP, Chakrabarty K. VFI-Based Power Management to Enhance the Lifetime of High-Performance 3D NoCs Acm Transactions On Design Automation of Electronic Systems. 23: 1-26. DOI: 10.1145/3092843  0.33
2017 Koneru A, Kannan S, Chakrabarty K. Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits Acm Journal On Emerging Technologies in Computing Systems. 13: 1-23. DOI: 10.1145/3041026  0.356
2017 Vartziotis F, Kavousianos X, Georgiou P, Chakrabarty K. A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi- $V_{\mathrm{ dd}}$ SoCs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1911-1924. DOI: 10.1109/Tcad.2017.2664062  0.408
2017 Wang R, Li Z, Kannan S, Chakrabarty K. Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1406-1419. DOI: 10.1109/Tcad.2016.2629422  0.476
2017 Wang R, Li G, Li R, Qian J, Chakrabarty K. ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1030-1042. DOI: 10.1109/Tcad.2016.2611515  0.481
2017 Das S, Doppa JR, Pande PP, Chakrabarty K. Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 719-732. DOI: 10.1109/Tcad.2016.2604288  0.336
2017 Ibrahim M, Chakrabarty K, Scott K. Synthesis of Cyberphysical Digital-Microfluidic Biochips for Real-Time Quantitative Analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 733-746. DOI: 10.1109/Tcad.2016.2600626  0.328
2017 Bhattacharjee S, Chatterjee S, Banerjee A, Ho T, Chakrabarty K, Bhattacharya BB. Adaptation of Biochemical Protocols to Handle Technology-Change for Digital Microfluidics Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 370-383. DOI: 10.1109/Tcad.2016.2585622  0.328
2017 Hu K, Dinh TA, Ho T, Chakrabarty K. Control-Layer Routing and Control-Pin Minimization for Flow-Based Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 55-68. DOI: 10.1109/Tcad.2016.2568198  0.325
2017 Wang R, Chakrabarty K. Tackling Test Challenges for Interposer-Based 2.5-D Integrated Circuits Ieee Design & Test. 34: 72-79. DOI: 10.1109/Mdat.2017.2705077  0.415
2017 Chakrabarty K. Quo Vadis Test? The Past, the Present, and the Future: No Longer a Necessary Evil Ieee Design & Test. 34: 93-95. DOI: 10.1109/Mdat.2017.2686584  0.43
2017 Shukla V, Hussin FA, Hamid NH, Ali NBZ, Chakrabarty K. Offline Error Detection in MEDA-Based Digital Microfluidic Biochips Using Oscillation-Based Testing Methodology Journal of Electronic Testing. 33: 621-635. DOI: 10.1007/S10836-017-5678-5  0.421
2016 Poddar S, Ghoshal S, Chakrabarty K, Bhattacharya BB. Error-Correcting Sample Preparation with Cyberphysical Digital Microfluidic Lab-on-Chip Acm Transactions On Design Automation of Electronic Systems. 22: 1-29. DOI: 10.1145/2898999  0.32
2016 Li Z, Ho TY, Chakrabarty K. Optimization of 3D digital microfluidic biochips for the multiplexed polymerase chain reaction Acm Transactions On Design Automation of Electronic Systems. 21. DOI: 10.1145/2811259  0.353
2016 Li T, Xie F, Liang X, Xu Q, Chakrabarty K, Jing N, Jiang L. A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1192-1205. DOI: 10.1109/Tcad.2015.2512909  0.419
2016 Hu K, Bhattacharya BB, Chakrabarty K. Fault diagnosis for leakage and blockage defects in flow-based microfluidic biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1179-1191. DOI: 10.1109/Tcad.2015.2488489  0.394
2016 Hu K, Ho TY, Chakrabarty K. Wash Optimization and Analysis for Cross-Contamination Removal under Physical Constraints in Flow-Based Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 559-572. DOI: 10.1109/Tcad.2015.2488485  0.32
2016 Jin S, Ye F, Zhang Z, Chakrabarty K, Gu X. Efficient Board-Level Functional Fault Diagnosis With Missing Syndromes Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 985-998. DOI: 10.1109/Tcad.2015.2481859  0.712
2016 Ye F, Firouzi F, Yang Y, Chakrabarty K, Tahoori MB. On-chip droop-induced circuit delay prediction based on support-vector machines Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 665-678. DOI: 10.1109/Tcad.2015.2474392  0.366
2016 Ye F, Zhang Z, Chakrabarty K, Gu X. Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 323-336. DOI: 10.1109/Tcad.2015.2459046  0.715
2016 Agrawal M, Chakrabarty K, Eklow B. A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 309-322. DOI: 10.1109/Tcad.2015.2459044  0.458
2016 Xiang D, Chakrabarty K, Fujiwara H. Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip Ieee Transactions On Computers. 65: 2767-2779. DOI: 10.1109/Tc.2015.2493548  0.474
2015 Mitra D, Ghoshal S, Rahaman H, Chakrabarty K, Bhattacharya BB. Offline washing schemes for residue removal in digital microfluidic biochips Acm Transactions On Design Automation of Electronic Systems. 21. DOI: 10.1145/2798726  0.324
2015 Duan Q, Koneru A, Zeng J, Chakrabarty K, Dispoto G. Accurate analysis and prediction of enterprise service-level performance Acm Transactions On Design Automation of Electronic Systems. 20. DOI: 10.1145/2757279  0.318
2015 Wang R, Chakrabarty K, Bhawmik S. Built-in self-test and test scheduling for interposer-based 2.5D IC Acm Transactions On Design Automation of Electronic Systems. 20. DOI: 10.1145/2757278  0.476
2015 Firouzi F, Ye F, Chakrabarty K, Tahoori MB. Aging-and variation-aware delay monitoring using representative critical path selection Acm Transactions On Design Automation of Electronic Systems. 20. DOI: 10.1145/2746237  0.345
2015 Roy S, Chakrabarti PP, Kumar S, Chakrabarty K, Bhattacharya BB. Layout-aware mixture preparation of biochemical fluids on application-specific digital microfluidic biochips Acm Transactions On Design Automation of Electronic Systems. 20. DOI: 10.1145/2714562  0.33
2015 Noia B, Panth S, Chakrabarty K, Lim SK. Scan test of die logic in 3-D ICs using TSV probing Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 317-330. DOI: 10.1109/Tvlsi.2014.2306951  0.823
2015 Deutsch S, Chakrabarty K. Test and debug solutions for 3D-stacked integrated circuits Proceedings - International Test Conference. 2015. DOI: 10.1109/TEST.2015.7342421  0.359
2015 Deutsch S, Chakrabarty K, Marinissen EJ. Robust Optimization of Test-Access Architectures Under Realistic Scenarios Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1873-1884. DOI: 10.1109/Tcad.2015.2432139  0.443
2015 Agrawal M, Chakrabarty K. Test-cost modeling and optimal test-flow selection of 3-D-stacked ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1523-1536. DOI: 10.1109/Tcad.2015.2419227  0.41
2015 Ye F, Zhang Z, Chakrabarty K, Gu X. Information-theoretic syndrome evaluation, statistical root-cause analysis, and correlation-based feature selection for guiding board-level fault diagnosis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1014-1026. DOI: 10.1109/Tcad.2015.2399438  0.719
2015 Vartziotis F, Kavousianos X, Chakrabarty K, Jain A, Parekhji R. Time-Division Multiplexing for Testing DVFS-Based SoCs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 668-681. DOI: 10.1109/Tcad.2015.2394462  0.467
2015 Agrawal M, Chakrabarty K, Widialaksono R. Reuse-based optimization for prebond and post-bond testing of 3-D-stacked ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 122-135. DOI: 10.1109/Tcad.2014.2369747  0.433
2015 Wang R, Chakrabarty K, Bhawmik S. Interconnect testing and test-path scheduling for interposer-based 2.5-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 136-149. DOI: 10.1109/Tcad.2014.2365097  0.51
2015 Luo Y, Bhattacharya BB, Ho TY, Chakrabarty K. Design and optimization of a cyberphysical digital-microfluidic biochip for the polymerase chain reaction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 29-42. DOI: 10.1109/Tcad.2014.2363396  0.33
2015 Pop P, Araci IE, Chakrabarty K. Continuous-flow biochips: Technology, physical-design methods, and testing Ieee Design and Test. 32: 8-19. DOI: 10.1109/Mdat.2015.2438152  0.325
2015 Dinh TA, Yamashita S, Ho TY, Chakrabarty K. Testing of digital microfluidic biochips with arbitrary layouts Proceedings - 2015 20th Ieee European Test Symposium, Ets 2014. DOI: 10.1109/ETS.2015.7138729  0.306
2014 Chakrabarty K, Agrawal M, Deutsch S, Noia B, Wang R, Ye F. Test and Design-for-Testability Solutions for 3D Integrated Circuits Ipsj Transactions On System Lsi Design Methodology. 7: 56-73. DOI: 10.2197/Ipsjtsldm.7.56  0.794
2014 Kuo CY, Shih CJ, Lu YC, Li JCM, Chakrabarty K. Testing of TSV-induced small delay faults for 3-d integrated circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 667-674. DOI: 10.1109/Tvlsi.2013.2250320  0.444
2014 Khursheed S, Shi K, Al-Hashimi BM, Wilson PR, Chakrabarty K. Delay test for diagnosis of power switches Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 197-206. DOI: 10.1109/Tvlsi.2013.2239319  0.369
2014 Zhang Z, Kavousianos X, Chakrabarty K, Tsiatouhas Y. Static power reduction using variation-tolerant and reconfigurable multi-mode power switches Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 13-26. DOI: 10.1109/Tvlsi.2012.2233505  0.699
2014 Hu K, Yu F, Ho TY, Chakrabarty K. Testing of flow-based microfluidic biochips: Fault modeling, test generation, and experimental demonstration Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1463-1475. DOI: 10.1109/Tcad.2014.2336215  0.458
2014 Wang R, Chakrabarty K, Eklow B. Scan-based testing of post-bond silicon interposer interconnects in 2.5-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1410-1423. DOI: 10.1109/Tcad.2014.2331336  0.332
2014 Mitra D, Roy S, Bhattacharjee S, Chakrabarty K, Bhattacharya BB. On-chip sample preparation for multiple targets using digital microfluidics Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1131-1144. DOI: 10.1109/Tcad.2014.2323200  0.321
2014 Wang R, Zhang Z, Kavousianos X, Tsiatouhas Y, Chakrabarty K. Built-in self-test, diagnosis, and repair of multimode power switches Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1231-1244. DOI: 10.1109/Tcad.2014.2314303  0.734
2014 Agrawal M, Richter M, Chakrabarty K. Test-delivery optimization in manycore SOCs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1067-1080. DOI: 10.1109/Tcad.2014.2311394  0.425
2014 Luo Y, Chakrabarty K, Ho TY. Biochemistry synthesis on a cyberphysical digital microfluidics platform under completion-time uncertainties in fluidic operations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 903-916. DOI: 10.1109/Tcad.2014.2303948  0.301
2014 Deutsch S, Chakrabarty K. Contactless pre-bond TSV test and diagnosis using ring oscillators and multiple voltage levels Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 774-785. DOI: 10.1109/Tcad.2014.2298198  0.436
2014 Noia B, Chakrabarty K. Retiming for delay recovery after DfT insertion on interdie paths in 3-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 464-475. DOI: 10.1109/Tcad.2013.2289857  0.804
2014 Ye F, Zhang Z, Chakrabarty K, Gu X. Board-level functional fault diagnosis using multikernel support vector machines and incremental learning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 279-290. DOI: 10.1109/Tcad.2013.2287184  0.709
2014 Hsieh YL, Ho TY, Chakrabarty K. Biochip synthesis and dynamic error recovery for sample preparation using digital microfluidics Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 183-196. DOI: 10.1109/Tcad.2013.2284010  0.305
2014 Richter M, Chakrabarty K. Optimization of test pin-count, test scheduling, and test access for NoC-based multicore SoCs Ieee Transactions On Computers. 63: 691-702. DOI: 10.1109/Tc.2013.82  0.47
2014 Ye F, Chakrabarty K, Zhang Z, Gu X. Information-theoretic framework for evaluating and guiding board-level functional-fault diagnosis Ieee Design and Test. 31: 65-75. DOI: 10.1109/Mdat.2014.2313080  0.678
2014 Li Z, Dinh TA, Ho TY, Chakrabarty K. Reliability-driven pipelined scan-like testing of digital microfluidic biochips Proceedings of the Asian Test Symposium. 57-62. DOI: 10.1109/ATS.2014.22  0.304
2014 Roy S, Bhattacharya BB, Ghoshal S, Chakrabarty K. High-throughput dilution engine for sample preparation on digital microfluidic biochips Iet Computers and Digital Techniques. 8: 163-171. DOI: 10.1049/Iet-Cdt.2013.0060  0.301
2014 Lien WC, Lee KJ, Hsieh TY, Chakrabarty K. Efficient LFSR Reseeding Based on Internal-Response Feedback Journal of Electronic Testing: Theory and Applications (Jetta). 30: 673-685. DOI: 10.1007/S10836-014-5482-4  0.431
2013 Xiang D, Li J, Chakrabarty K, Lin X. Test compaction for small-delay defects using an effective path selection scheme Acm Transactions On Design Automation of Electronic Systems. 18. DOI: 10.1145/2491477.2491488  0.479
2013 Peng K, Yilmaz M, Chakrabarty K, Tehranipoor M. Crosstalk- and process variations-aware high-quality tests for small-delay defects Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1129-1142. DOI: 10.1109/Tvlsi.2012.2205026  0.425
2013 Luo Y, Chakrabarty K, Ho TY. Real-time error recovery in cyberphysical digital-microfluidic biochips using a compact dictionary Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1839-1852. DOI: 10.1109/Tcad.2013.2277980  0.318
2013 Bao F, Peng K, Tehranipoor M, Chakrabarty K. Generation of effective 1-detect TDF patterns for detecting small-delay defects Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1583-1594. DOI: 10.1109/Tcad.2013.2266374  0.354
2013 Luo Y, Chakrabarty K. Design of pin-constrained general-purpose Digital microfluidic biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1307-1320. DOI: 10.1109/Tcad.2013.2260192  0.335
2013 Karimi N, Chakrabarty K. Detection, diagnosis, and recovery from Clock-Domain Crossing failures in multiclock SoCs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1395-1408. DOI: 10.1109/Tcad.2013.2255127  0.39
2013 Ye F, Zhang Z, Chakrabarty K, Gu X. Board-level functional fault diagnosis using artificial neural networks, support-vector machines, and weighted-majority voting Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 723-736. DOI: 10.1109/Tcad.2012.2234827  0.716
2013 Noia B, Chakrabarty K. Pre-bond probing of through-silicon vias in 3-D stacked ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 547-558. DOI: 10.1109/Tcad.2012.2226455  0.813
2013 Lien WC, Lee KJ, Hsieh TY, Chakrabarty K, Wu YH. Counter-based output selection for test response compaction Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 152-164. DOI: 10.1109/Tcad.2012.2214479  0.416
2013 Luo Y, Chakrabarty K, Ho TY. Error recovery in cyberphysical digital microfluidic biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 59-72. DOI: 10.1109/Tcad.2012.2211104  0.308
2013 Bao F, Peng K, Yilmaz M, Chakrabarty K, Winemberg L, Tehranipoor M. Efficient pattern generation for small-delay defects using selection of critical faults Journal of Electronic Testing: Theory and Applications (Jetta). 29: 35-48. DOI: 10.1007/S10836-012-5345-9  0.376
2012 Shih C, Hsu C, Kuo C, Li J, Rau J, Chakrabarty K. Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC Active and Passive Electronic Components. 2012: 1-10. DOI: 10.1155/2012/763572  0.395
2012 Zamani M, Tahoori MB, Chakrabarty K. Ping-pong test: Compact test vector generation for reversible circuits Proceedings of the Ieee Vlsi Test Symposium. 164-169. DOI: 10.1109/VTS.2012.6231097  0.368
2012 Fang H, Chakrabarty K, Jas A, Patil S, Tirumurti C. Functional test-sequence grading at register-transfer level Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 1890-1894. DOI: 10.1109/Tvlsi.2011.2163651  0.743
2012 Jiang L, Xu Q, Chakrabarty K, Mak TM. Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint Ieee Transactions On Very Large Scale Integration Systems. 20: 1621-1633. DOI: 10.1109/Tvlsi.2011.2160410  0.468
2012 Zhao Y, Chakrabarty K, Sturmer R, Pamula VK. Optimization Techniques for the Synchronization of Concurrent Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 1132-1145. DOI: 10.1109/Tvlsi.2011.2145397  0.322
2012 Zhang Z, Wang Z, Gu X, Chakrabarty K. Physical-Defect Modeling and Optimization for Fault-Insertion Test Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 20: 723-736. DOI: 10.1109/Tvlsi.2011.2114681  0.787
2012 Kavousianos X, Chakrabarty K, Jain A, Parekhji R. Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1754-1766. DOI: 10.1109/Tcad.2012.2203600  0.433
2012 Fang H, Chakrabarty K, Wang Z, Gu X. Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster–Shafer Theory Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1586-1599. DOI: 10.1109/Tcad.2012.2198884  0.734
2012 Zhao Y, Chakrabarty K. Simultaneous Optimization of Droplet Routing and Control-Pin Mapping to Electrodes in Digital Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 242-254. DOI: 10.1109/Tcad.2011.2177836  0.309
2012 Fang H, Chakrabarty K, Wang Z, Gu X. Reproduction and Detection of Board-Level Functional Failure Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 630-643. DOI: 10.1109/Tcad.2011.2175391  0.736
2012 Chakrabarty K. Towards more digital content in wireless systems [From the EiC] Ieee Design & Test of Computers. 29: 4-4. DOI: 10.1109/Mdt.2012.2228601  0.304
2012 Chakrabarty K. Towards smarter silicon and data-driven design of integrated circuits [From the EIC] Ieee Design & Test of Computers. 29: 4-5. DOI: 10.1109/Mdt.2012.2223511  0.365
2012 Chakrabarty K. Looking ahead at the role of electronic design automation in synthetic biology [From the EIC] Ieee Design & Test of Computers. 29: 4-4. DOI: 10.1109/Mdt.2012.2199612  0.311
2012 Chakrabarty K, Deutsch S, Thapliyal H, Ye F. TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test Ieee International Reliability Physics Symposium Proceedings. DOI: 10.1109/IRPS.2012.6241859  0.306
2011 Kavousianos X, Tenentes V, Chakrabarty K, Kalligeros E. Defect-Oriented LFSR Reseeding to Target Unmodeled Defects Using Stuck-at Test Sets Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 2330-2335. DOI: 10.1109/Tvlsi.2010.2079961  0.442
2011 Chen Z, Chakrabarty K, Xiang D. MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1762-1767. DOI: 10.1109/Tcad.2011.2162237  0.463
2011 Noia B, Chakrabarty K, Goel SK, Marinissen EJ, Verbree J. Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 1705-1718. DOI: 10.1109/Tcad.2011.2160177  0.824
2011 Zhao Y, Xu T, Chakrabarty K. Broadcast Electrode-Addressing and Scheduling Methods for Pin-Constrained Digital Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 986-999. DOI: 10.1109/Tcad.2011.2116250  0.339
2011 Kavousianos X, Chakrabarty K. Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 787-791. DOI: 10.1109/Tcad.2010.2101750  0.42
2011 Yilmaz M, Tehranipoor M, Chakrabarty K. A Metric to Target Small-Delay Defects in Industrial Circuits Ieee Design & Test of Computers. 28: 52-61. DOI: 10.1109/Mdt.2011.26  0.619
2011 Noia B, Chakrabarty K. Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips Iet Computers & Digital Techniques. 5: 186. DOI: 10.1049/Iet-Cdt.2009.0111  0.812
2011 Zhao Y, Chakrabarty K, Bhattacharya BB. Testing of Low-cost Digital Microfluidic Biochips with Non-Regular Array Layouts Journal of Electronic Testing. 28: 243-255. DOI: 10.1007/S10836-011-5266-Z  0.459
2011 Mitra D, Ghoshal S, Rahaman H, Chakrabarty K, Bhattacharya BB. Test Planning in Digital Microfluidic Biochips Using Efficient Eulerization Techniques Journal of Electronic Testing. 27: 657-671. DOI: 10.1007/S10836-011-5239-2  0.468
2011 Noia B, Chakrabarty K, Marinissen EJ. Optimization Methods for Post-Bond Testing of 3D Stacked ICs Journal of Electronic Testing. 28: 103-120. DOI: 10.1007/S10836-011-5233-8  0.816
2010 Yang Zhao, Chakrabarty K. Digital Microfluidic Logic Gates and Their Application to Built-in Self-Test of Lab-on-Chip. Ieee Transactions On Biomedical Circuits and Systems. 4: 250-62. PMID 23853371 DOI: 10.1109/Tbcas.2010.2048567  0.454
2010 Sabbineni H, Chakrabarty K. An Energy-Efficient Data Delivery Scheme for Delay-Sensitive Traffic in Wireless Sensor Networks International Journal of Distributed Sensor Networks. 6: 792068-792068. DOI: 10.1155/2010/792068  0.776
2010 Sabbineni H, Chakrabarty K. Datacollection in Event-Driven Wireless Sensor Networks with Mobile Sinks International Journal of Distributed Sensor Networks. 6: 402680. DOI: 10.1155/2010/402680  0.771
2010 Zhao Y, Xu T, Chakrabarty K. Integrated control-path design and error recovery in the synthesis of digital microfluidic lab-on-chip Acm Journal On Emerging Technologies in Computing Systems. 6: 1-28. DOI: 10.1145/1777401.1777404  0.32
2010 Chakrabarty K. Design Automation and Test Solutions for Digital Microfluidic Biochips Ieee Transactions On Circuits and Systems I: Regular Papers. 57: 4-17. DOI: 10.1109/Tcsi.2009.2038976  0.376
2010 Roy S, Bhattacharya BB, Chakrabarty K. Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1696-1708. DOI: 10.1109/Tcad.2010.2061790  0.318
2010 Khursheed S, Al-Hashimi BM, Chakrabarty K, Harrod P. Gate-Sizing-Based Single $V_{\rm dd}$ Test for Bridge Defects in Multivoltage Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1409-1421. DOI: 10.1109/Tcad.2010.2059310  0.468
2010 Chakrabarty K, Fair RB, Zeng J. Design Tools for Digital Microfluidic Biochips: Toward Functional Diversification and More Than Moore Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1001-1017. DOI: 10.1109/Tcad.2010.2049153  0.356
2010 Yilmaz M, Chakrabarty K, Tehranipoor M. Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 760-773. DOI: 10.1109/Tcad.2010.2043591  0.632
2010 Xu T, Chakrabarty K, Pamula VK. Defect-Tolerant Design and Optimization of a Digital Microfluidic Biochip for Protein Crystallization Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 552-565. DOI: 10.1109/Tcad.2010.2042888  0.312
2010 Chakrabarty K. Increasing yield and reliability through postsilicon tuning Ieee Design & Test of Computers. 27: 2-2. DOI: 10.1109/Mdt.2010.135  0.35
2010 Yilmaz M, Chakrabarty K, Tehranipoor M. Adaptation and Evaluation of the Output-Deviations Metric to Target Small-Delay Defects in Industrial Circuits Ieee Design & Test of Computers. DOI: 10.1109/Mdt.2010.114  0.654
2010 Wu X, Chen Y, Chakrabarty K, Xie Y. Test-access mechanism optimization for core-based three-dimensional SOCs Microelectronics Journal. 41: 601-615. DOI: 10.1016/J.Mejo.2010.06.015  0.465
2010 Zhao Y, Chakrabarty K. Fault Diagnosis in Lab-on-Chip Using Digital Microfluidic Logic Gates Journal of Electronic Testing. 27: 69-83. DOI: 10.1007/S10836-010-5190-7  0.425
2010 Fang H, Chakrabarty K, Fujiwara H. RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences Journal of Electronic Testing. 26: 151-164. DOI: 10.1007/S10836-009-5135-1  0.763
2009 Tao Xu, Chakrabarty K. Fault modeling and functional test methods for digital microfluidic biochips. Ieee Transactions On Biomedical Circuits and Systems. 3: 241-53. PMID 23853245 DOI: 10.1109/Tbcas.2009.2022173  0.429
2009 Wu X, Falkenstern P, Chakrabarty K, Xie Y. Scan-chain design and optimization for three-dimensional integrated circuits Acm Journal On Emerging Technologies in Computing Systems. 5: 1-26. DOI: 10.1145/1543438.1543442  0.35
2009 Xu Q, Zhang Y, Chakrabarty K. SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects Acm Transactions On Design Automation of Electronic Systems. 14: 1-27. DOI: 10.1145/1455229.1455233  0.478
2009 Xu T, Chakrabarty K. Design-for-testability for digital microfluidic biochips Proceedings of the Ieee Vlsi Test Symposium. 309-314. DOI: 10.1109/VTS.2009.16  0.306
2009 Fang H, Chakrabarty K, Jas A, Patil S, Tirumurti C. RT-level deviation-based grading of functional test sequences Proceedings of the Ieee Vlsi Test Symposium. 264-269. DOI: 10.1109/VTS.2009.12  0.319
2009 Bahukudumbi S, Chakrabarty K. Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 1730-1741. DOI: 10.1109/Tvlsi.2008.2006679  0.81
2009 Bahukudumbi S, Ozev S, Chakrabarty K, Iyengar V. Wafer-level defect screening for big-D/small-A mixed-signal SoCs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 17: 587-592. DOI: 10.1109/Tvlsi.2008.2006075  0.787
2009 Wang Z, Chakrabarty K, Wang S. Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1251-1264. DOI: 10.1109/Tcad.2009.2021731  0.83
2009 Wang Z, Fang H, Chakrabarty K, Bienek M. Deviation-Based LFSR Reseeding for Test-Data Compression Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 259-271. DOI: 10.1109/Tcad.2008.2009166  0.8
2009 Bahukudumbi S, Chakrabarty K. Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 111-120. DOI: 10.1109/Tcad.2008.2009150  0.462
2009 Goel S, Marinissen EJ, Sehgal A, Chakrabarty K. Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling Ieee Transactions On Computers. 58: 409-423. DOI: 10.1109/Tc.2008.169  0.43
2009 Kaminska B, Chakrabarty K. Guest Editorial—Selected Papers from the IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW), 2008 Ieee Transactions On Biomedical Circuits and Systems. 3: 193-194. DOI: 10.1109/Tbcas.2009.2025648  0.325
2009 Lee HS, Chakrabarty K. Test Challenges for 3D Integrated Circuits Ieee Design & Test of Computers. 26: 26-35. DOI: 10.1109/Mdt.2009.125  0.345
2009 Yu TE, Yoneda T, Chakrabarty K, Fujiwara H. Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 793-798. DOI: 10.1109/ASPDAC.2009.4796577  0.351
2009 Mao V, Thusu V, Dwyer C, Chakrabarty K. Connecting fabrication defects to fault models and simulation program with integrated circuit emphasis simulations for DNA self-assembled nanoelectronics Iet Computers & Digital Techniques. 3: 553. DOI: 10.1049/Iet-Cdt.2008.0136  0.32
2009 Zhao Y, Chakrabarty K. On-Line Testing of Lab-on-Chip Using Reconfigurable Digital-Microfluidic Compactors International Journal of Parallel Programming. 37: 370-388. DOI: 10.1007/S10766-009-0103-Z  0.447
2008 Tao Xu, Chakrabarty K, Fei Su. Defect-aware high-level synthesis and module placement for microfluidic biochips. Ieee Transactions On Biomedical Circuits and Systems. 2: 50-62. PMID 23852633 DOI: 10.1109/Tbcas.2008.918283  0.345
2008 Xu T, Chakrabarty K. Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips Acm Journal On Emerging Technologies in Computing Systems. 4: 1-24. DOI: 10.1145/1389089.1389091  0.343
2008 Sehgal A, Bahukudumbi S, Chakrabarty K. Power-aware SoC test planning for effective utilization of port-scalable testers Acm Transactions On Design Automation of Electronic Systems. 13: 1-19. DOI: 10.1145/1367045.1367062  0.814
2008 Su F, Chakrabarty K. High-level synthesis of digital microfluidic biochips Acm Journal On Emerging Technologies in Computing Systems. 3. DOI: 10.1145/1324177.1324178  0.352
2008 Wang Z, Chakrabarty K. Test Data Compression Using Selective Encoding of Scan Slices Ieee Transactions On Very Large Scale Integration Systems. 16: 1429-1440. DOI: 10.1109/Tvlsi.2008.2000674  0.825
2008 Xiang D, Zhao Y, Chakrabarty K, Fujiwara H. A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 999-1012. DOI: 10.1109/Tcad.2008.923260  0.462
2008 Samii S, Selkala M, Larsson E, Chakrabarty K, Peng Z. Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 973-977. DOI: 10.1109/Tcad.2008.917974  0.426
2008 Xu T, Chakrabarty K. A Droplet-Manipulation Method for Achieving High-Throughput in Cross-Referencing-Based Digital Microfluidic Biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1905-1917. DOI: 10.1109/Tcad.2008.2006086  0.336
2008 Wang Z, Chakrabarty K. Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 352-365. DOI: 10.1109/Tcad.2007.907228  0.828
2008 Paik PY, Pamula VK, Chakrabarty K. A digital-microfluidic approach to chip cooling Ieee Design and Test of Computers. 25: 372-391. DOI: 10.1109/Mdt.2008.87  0.328
2008 Yu TE, Yoneda T, Chakrabarty K, Fujiwara H. Thermal-aware test access mechanism and wrapper design optimization for system-on-chips Ieice Transactions On Information and Systems. 2440-2448. DOI: 10.1093/Ietisy/E91-D.10.2440  0.404
2008 Badereddine N, Wang Z, Girard P, Chakrabarty K, Virazel A, Pravossoudovitch S, Landrault C. A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction Journal of Electronic Testing. 24: 353-364. DOI: 10.1007/S10836-007-5053-Z  0.822
2007 Tao Xu, Chakrabarty K. Parallel scan-like test and multiple-defect diagnosis for digital microfluidic biochips. Ieee Transactions On Biomedical Circuits and Systems. 1: 148-58. PMID 23851669 DOI: 10.1109/Tbcas.2007.909025  0.451
2007 Xu T, Hwang WL, Su F, Chakrabarty K. Automated design of pin-constrained digital microfluidic biochips under droplet-interference constraints Acm Journal On Emerging Technologies in Computing Systems. 3: 14. DOI: 10.1145/1295231.1295235  0.36
2007 Li L, Wang Z, Chakrabarty K. Scan-BIST based on cluster analysis and the encoding of repeating sequences Acm Transactions On Design Automation of Electronic Systems. 12: 1-21. DOI: 10.1145/1188275.1188279  0.811
2007 Bahukudumbi S, Chakrabarty K. Wafer-Level Modular Testing of Core-Based SoCs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 15: 1144-1154. DOI: 10.1109/Tvlsi.903943  0.821
2007 Xu Q, Nicolici N, Chakrabarty K. Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 1539-1547. DOI: 10.1109/Tcad.2007.893556  0.441
2007 Sehgal A, Chakrabarty K. Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs Ieee Transactions On Computers. 56: 120-133. DOI: 10.1109/Tc.2007.15  0.443
2007 Chakrabarty K, Thewes R. Guest Editors' Introduction: Biochips and Integrated Biosensor Platforms Ieee Design & Test of Computers. 24: 8-9. DOI: 10.1109/Mdt.2007.15  0.31
2007 Zou Y, Chakrabarty K. Redundancy Analysis and a Distributed Self-Organization Protocol for Fault-Tolerant Wireless Sensor Networks International Journal of Distributed Sensor Networks. 3: 243-272. DOI: 10.1080/15501320600781078  0.3
2007 Su F, Hwang W, Mukherjee A, Chakrabarty K. Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips Journal of Electronic Testing. 23: 219-233. DOI: 10.1007/S10836-006-0554-8  0.418
2007 Wang Z, Chakrabarty K. Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics Journal of Electronic Testing. 23: 145-161. DOI: 10.1007/S10836-006-0550-Z  0.801
2006 Su F, Chakrabarty K. Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy Acm Journal On Emerging Technologies in Computing Systems. 2: 104-128. DOI: 10.1145/1148015.1148017  0.355
2006 Su F, Ozev S, Chakrabarty K. Concurrent testing of digital microfluidics-based biochips Acm Transactions On Design Automation of Electronic Systems. 11: 442-464. DOI: 10.1145/1142155.1142164  0.481
2006 Su F, Chakrabarty K. Defect tolerance based on graceful degradation and dynamic reconfiguration for digital microfluidics-based biochips Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2944-2953. DOI: 10.1109/Tcad.2006.882480  0.34
2006 Rosinger P, Al-Hashimi B, Chakrabarty K. Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 2502-2512. DOI: 10.1109/Tcad.2006.873898  0.418
2006 Su F, Chakrabarty K, Fair R. Microfluidics-Based Biochips: Technology Issues, Implementation Platforms, and Design-Automation Challenges Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 211-223. DOI: 10.1109/Tcad.2005.855956  0.384
2006 Zhang Y, Chakrabarty K. A unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 111-125. DOI: 10.1109/Tcad.2005.852657  0.387
2006 Würtenberger A, Rosinger P, Al-Hashimi B, Chakrabarty K. Cost model driven test resource partitioning for SoCs Electronics Letters. 42: 915. DOI: 10.1049/El:20061556  0.372
2005 Chakrabarty K, Zeng J. Design automation for microfluidics-based biochips Acm Journal On Emerging Technologies in Computing Systems. 1: 186-223. DOI: 10.1145/1116696.1116698  0.334
2005 Swaminathan V, Chakrabarty K. Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems Acm Transactions On Embedded Computing Systems (Tecs). 4: 141-167. DOI: 10.1145/1053271.1053277  0.77
2005 Liu C, Chakrabarty K. Design and analysis of compact dictionaries for diagnosis in scan-BIST Ieee Transactions On Very Large Scale Integration Systems. 13: 979-984. DOI: 10.1109/Tvlsi.2005.853624  0.543
2005 Tehranipoor M, Nourani M, Chakrabarty K. Nine-coded compression technique for testing embedded cores in SoCs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 719-730. DOI: 10.1109/Tvlsi.2005.844311  0.417
2005 Chakrabarty K, Iyengar V, Krasniewski MD. Test Planning for modular testing of hierarchical SOCs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 435-447. DOI: 10.1109/Tcad.2004.842816  0.443
2005 Sabbineni H, Chakrabarty K. Location-aided flooding: an energy-efficient data dissemination protocol for wireless-sensor networks Ieee Transactions On Computers. 54: 36-46. DOI: 10.1109/Tc.2005.8  0.768
2005 Su F, Ozev S, Chakrabarty K. Ensuring the operational health of droplet-based microelectrofluidic biosensor systems Ieee Sensors Journal. 5: 763-772. DOI: 10.1109/Jsen.2005.848127  0.364
2005 Sehgal A, Ozev S, Chakrabarty K. A flexible design methodology for analog test wrappers in mixed-signal SOCs Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 2005: 137-142. DOI: 10.1109/ICCD.2005.8  0.327
2005 Sehgal A, Chakrabarty K. Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 2005: 88-93. DOI: 10.1109/ICCAD.2005.1560045  0.345
2005 Sehgal A, Liu F, Ozev S, Chakrabarty K. Test planning for mixed-signal SOCs with wrapped analog cores Proceedings -Design, Automation and Test in Europe, Date '05. 50-55. DOI: 10.1109/DATE.2005.303  0.337
2004 Sabbineni H, Chakrabarty K. A Survey of Energy-Efficient Self-Organization and Data Dissemination Protocols for Ad Hoc Sensor Networks Sensor Letters. 2: 194-204. DOI: 10.1166/Sl.2004.055  0.759
2004 Zhang Y, Chakrabarty K. Dynamic adaptation for fault tolerance and power management in embedded real-time systems Acm Transactions On Embedded Computing Systems. 3: 336-360. DOI: 10.1145/993396.993402  0.385
2004 Sehgal A, Iyengar V, Chakrabarty K. SOC test planning using virtual test access architectures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 12: 1263-1276. DOI: 10.1109/Tvlsi.2004.834228  0.698
2004 Swaminathan V, Chakrabarty K. Network flow techniques for dynamic voltage scaling in hard real-time systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1385-1398. DOI: 10.1109/Tcad.2004.833621  0.784
2004 Liu C, Chakrabarty K. Identification of Error-Capturing Scan Cells in Scan-BIST With Applications to System-on-Chip Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1447-1459. DOI: 10.1109/Tcad.2004.833620  0.567
2004 Li L, Chakrabarty K. Test Set Embedding for Deterministic BIST Using a Reconfigurable Interconnection Network Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1289-1305. DOI: 10.1109/Tcad.2004.831593  0.479
2004 Zhang T, Chakrabarty K, Fair R. Behavioral Modeling and Performance Evaluation of Microelectrofluidics-Based PCR Systems Using SystemC Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 843-858. DOI: 10.1109/Tcad.2004.828115  0.576
2004 Liu C, Chakrabarty K. Compact dictionaries for fault diagnosis in scan-BIST Ieee Transactions On Computers. 53: 775-780. DOI: 10.1109/Tc.2004.4  0.354
2004 Tehranipour M, Nourani M, Chakrabarty k. Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 2: 1284-1289. DOI: 10.1109/DATE.2004.1269072  0.339
2004 Sehgal A, Chakrabarty K. Efficient modular testing of SOCs using dual-speed TAM architectures Proceedings - Design, Automation and Test in Europe Conference and Exhibition. 1: 422-427. DOI: 10.1109/DATE.2004.1268883  0.32
2004 Chandra A, Chakrabarty K. Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes Journal of Electronic Testing. 20: 199-212. DOI: 10.1023/B:Jett.0000023682.41142.44  0.653
2004 Su F, Ozev S, Chakrabarty K. Test planning and test resource optimization for droplet-based microfluidic systems Proceedings - Ninth Ieee European Test Symposium, Ets 2004. 72-77. DOI: 10.1007/S10836-005-1256-3  0.419
2004 Li L, Chakrabarty K. On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression Journal of Electronic Testing. 20: 667-670. DOI: 10.1007/S10677-004-4254-0  0.316
2004 Goessel M, Chakrabarty K, Ocheretnij V, Leininger A. A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST* Journal of Electronic Testing. 20: 611-622. DOI: 10.1007/S10677-004-4249-X  0.431
2003 Li L, Chakrabarty K, Touba NA. Test Data Compression Using Dictionaries with Selective Entries and Fixed-Length Indices Acm Transactions On Design Automation of Electronic Systems. 8: 470-490. DOI: 10.1145/944027.944032  0.458
2003 Chakrabarty K. A synthesis-for-transparency approach for hierarchical and system-on-a-chip test Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 11: 167-179. DOI: 10.1109/Tvlsi.2003.810784  0.441
2003 Das SR, Sudarma M, Assaf MH, Petriu EM, Jone WB, Chakrabarty K, Şhinoǧlu M. Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets Ieee Transactions On Instrumentation and Measurement. 52: 1363-1380. DOI: 10.1109/Tim.2003.818547  0.476
2003 Chakrabarty K, Seuring M. Space compaction of test responses using orthogonal transmission functions Ieee Transactions On Instrumentation and Measurement. 52: 1353-1362. DOI: 10.1109/Tim.2003.818542  0.423
2003 Swaminathan V, Chakrabarty K. Energy-conscious, deterministic I/O device scheduling in hard real-time systems Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 847-858. DOI: 10.1109/Tcad.2003.814245  0.767
2003 Liu C, Chakrabarty K. Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 593-604. DOI: 10.1109/Tcad.2003.810739  0.614
2003 Iyengar V, Chakrabarty K, Marinissen EJ. Efficient test access mechanism optimization for system-on-chip Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 635-643. DOI: 10.1109/Tcad.2003.810737  0.462
2003 Chandra A, Chakrabarty K. A unified approach to reduce soc test data volume, scan power and testing time Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 352-362. DOI: 10.1109/Tcad.2002.807895  0.661
2003 Iyengar V, Chakrabarty K, Marinissen EJ. Test Access Mechanism Optimization Test Scheduling, and Tester Data Volume Reduction for System-on-Chip Ieee Transactions On Computers. 52: 1619-1632. DOI: 10.1109/Tc.2003.1252857  0.465
2003 Chandra A, Chakrabarty K. Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes Ieee Transactions On Computers. 52: 1076-1088. DOI: 10.1109/Tc.2003.1223641  0.616
2002 Bhattacharya B, Dmitriev A, Gossel M, Chakrabarty K. Synthesis of single-output space compactors for scan-based sequential circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1171-1179. DOI: 10.1109/Tcad.2002.802275  0.449
2002 Iyengar V, Chakrabarty K. System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 1088-1094. DOI: 10.1109/Tcad.2002.801102  0.448
2002 Zhang T, Chakrabarty K, Fair R. Design of reconfigurable composite microsystems based on hardware/software codesign principles Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 987-995. DOI: 10.1109/Tcad.2002.800455  0.313
2002 Chandra A, Chakrabarty K. Test data compression and decompression based on internal scan chains and Golomb coding Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 715-722. DOI: 10.1109/Tcad.2002.1004315  0.631
2002 Iyengar V, Chakrabarty K. Test bus sizing for system-on-a-chip Ieee Transactions On Computers. 51: 449-459. DOI: 10.1109/Tc.2002.1004585  0.455
2002 Chakrabarty K, Marinissen EJ. How Useful are the ITC 02 SoC Test Benchmarks Ieee Design & Test of Computers. 19: 120. DOI: 10.1109/Mdt.2002.10029  0.389
2002 Chandra A, Chakrabarty K. Low-power scan testing and test data compression for system-on-a-chip Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 21: 597-604. DOI: 10.1109/43.998630  0.643
2002 Das SR, Liang JY, Petriu EM, Assaf MH, Jone WB, Chakrabarty K. Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering Ieee Transactions On Instrumentation and Measurement. 51: 150-172. DOI: 10.1109/19.989919  0.428
2002 Zhang T, Chakrabarty K, Fair RB. Integrated hierarchical design of microelectrofluidic systems using SystemC Microelectronics Journal. 33: 459-470. DOI: 10.1016/S0026-2692(01)00157-4  0.547
2001 Chandra A, Chakrabarty K, Hansen MC. Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters Vlsi Design. 12: 475-486. DOI: 10.1155/2001/75139  0.675
2001 Chakrabarty K. Optimal test access architectures for system-on-a-chip Acm Transactions On Design Automation of Electronic Systems (Todaes). 6: 26-49. DOI: 10.1145/371254.371258  0.471
2001 Zhang T, Cao F, Dewey AM, Fair RB, Chakrabarty K. Corrections to "Performance analysis of microelectrofluidic systems using hierarchical modeling and simulation" Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 48: 749-749. DOI: 10.1109/Tcsii.2001.958347  0.537
2001 Zhang T, Cao F, Dewey AM, Fair RB, Chakrabarty K. Performance analysis of microelectrofluidic systems using hierarchical modeling and simulation Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 48: 482-491. DOI: 10.1109/82.938358  0.571
2001 Chandra A, Chakrabarty K. Test resource partitioning for SOCs Ieee Design & Test of Computers. 18: 80-91. DOI: 10.1109/54.953275  0.647
2001 Ding J, Chakrabarty K, Fair RB. Scheduling of microfluidic operations for reconfigurable two-dimensional electrowetting arrays Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 1463-1468. DOI: 10.1109/43.969439  0.309
2001 Chandra A, Chakrabarty K. System-on-a-chip test-data compression and decompression architectures based on Golomb codes Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 20: 355-368. DOI: 10.1109/43.913754  0.64
2001 Swaminathan S, Chakrabarty K. Journal of Electronic Testing. 17: 529-542. DOI: 10.1023/A:1012872706123  0.483
2001 Swaminathan V, Chakrabarty K. Real-time task scheduling for energy-aware embedded systems Journal of the Franklin Institute. 338: 729-750. DOI: 10.1016/S0016-0032(01)00021-7  0.764
2000 Chakrabarty K, Murray B, Iyengar V. Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 8: 633-636. DOI: 10.1109/92.894170  0.462
2000 Chakrabarty K. Test scheduling for core-based systems using mixed-integer linear programming Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 1163-1174. DOI: 10.1109/43.875306  0.409
2000 Das SR, Barakat TF, Petriu EM, Assaf MH, Chakrabarty K. Space compression revisited Ieee Transactions On Instrumentation and Measurement. 49: 690-705. DOI: 10.1109/19.850416  0.433
2000 Chakrabarty K, Das SR. Test-set embedding based on width compression for mixed-mode BIST Ieee Transactions On Instrumentation and Measurement. 49: 671-678. DOI: 10.1109/19.850413  0.433
1999 Iyengar V, Chakrabarty K, Murray BT. Journal of Electronic Testing. 15: 97-114. DOI: 10.1023/A:1008384201996  0.487
1998 Chakrabarty K, Hayes J. Zero-aliasing space compaction of test responses using multiple parity signatures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 6: 309-313. DOI: 10.1109/92.678893  0.612
1998 Chakrabarty K, Murray B. Design of built-in test generator circuits using width compression Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 1044-1051. DOI: 10.1109/43.728923  0.422
1998 Chakrabarty K. Zero-aliasing space compaction using linear compactors with bounded overhead Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 17: 452-457. DOI: 10.1109/43.703941  0.362
1998 Iyengar V, Chakrabarty K, Murray B. Huffman encoding of test sets for sequential circuits Ieee Transactions On Instrumentation and Measurement. 47: 21-25. DOI: 10.1109/19.728782  0.474
1998 Chakrabarty K, Murray B, Hayes J. Optimal zero-aliasing space compaction of test responses Ieee Transactions On Computers. 47: 1171-1187. DOI: 10.1109/12.736427  0.584
1997 Chakrabarty K, Hayes J. On the quality of accumulator-based compaction of test responses Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 16: 916-922. DOI: 10.1109/43.644618  0.6
1997 Iyengar V, Chakrabarty K. An efficient finite-state machine implementation of Huffman decoders Information Processing Letters. 64: 271-275. DOI: 10.1016/S0020-0190(97)00176-2  0.349
1996 Chakrabarty K, Hayes J. Test response compaction using multiplexed parity trees Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 15: 1399-1408. DOI: 10.1109/43.543772  0.648
1996 Chakrabarty K, Hayes JP. Balance testing and balance-testable design of logic circuits Journal of Electronic Testing. 8: 71-86. DOI: 10.1007/Bf00136077  0.661
1995 Chakrabarty K, Hayes J. Cumulative balance testing of logic circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 3: 72-83. DOI: 10.1109/92.365455  0.651
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