David J. Allstot - US grants

This proposal combines circuit design, material growth and characterization, and device test capabilities of Oregon State University with the industrial circuit fabrication facilities of TriQuint Semiconductor, Inc. to build and test high speed devices and circuits from strained pseudomorphic III-V ternary materials. InGaAs/GaAs and InGaAs/AlGaAs pseudomorphic HEMT structures will be grown by molecular beam epitaxy at OSU using a variety of structural parameters to optimize material properties. In particular, the investigators propose to grow ordered ternary material by growing binary superlattices; they will also grow both n- and p- channel material. The MBE material will be extensively characterized by optical and electrical measurements. The wafers will then be processed into a variety of test devices and integrated circuits at TriQuint at no cost to the National Science Foundation, after which the device and circuit performance will be fully tested and characterized using the facilities of both TriQuint and OSU. Based on the complete characterization new mask sets will then be designed at OSU and fabricated at Tektronix in order to optimize circuit performance.

This project combines analog circuit design and CAD to produce digital circuits that can operate at substantially reduced voltages, which will result in lower power consumption. The project has introduced the QuadRail logic family, which allows voltage control of transistor thresholds to maintain constant logic thresholds. Use of this family permits lower supply voltages because of the tighter control of device thresholds. However, use of this family requires optimization of individual digital cells, new device layout methods, and new strategies for floorplanning, placement, and routing. The research in this project is exploring all of these optimization areas, and is producing a battery powered demonstration system for speech signal processing.

This project studies the integration of heterogeneous resources into a system-on-chip (SOC) solution. Heterogeneous SOC integration supports the fabrication of RF, analog, high performance digital, and re-configurable subsystems within a single piece of silicon, and includes issues of simulation, design, integration, test, and education. An example SOC is a human/machine transducer chip that provides a speech recognition interface to a ubiquitous wireless network. Such a system represents a standard interface modality. Multiple topics are being researched including low-power speaker identification, speech processing algorithms, and hardware implementations. Low power, high performance wireless protocols are also being developed to support the asymmetric communication loads, sending low bandwidth control messages produced from the recognized speech and receiving high-bandwidth information return for visual, audio, and other feedback to the user.

Interconnect has been recognized one of ten hardest problems in nano technologies. A basic observation underlying this project is that nano-interconnect issues are much similar to that in real-world communication. Much research has been conducted to ensure the reliable, fast and secure communication over a noisy and stochastic environment. Therefore, the research is exploiting communication-theoretic principles and developing innovative signaling concepts in solving the stochastic nature of nano interconnect. The primary focus is on nano silicon technologies in CMOS with feature sizes below 100nm, and the goal is to explore ways to achieve reliable and fast signaling over the noisy and stochastically limited nano-interconnect environment. The specific objectives are
1. to develop realistic-yet-simple communication models for various nano interconnect scenarios,
2. To study fundamental signaling limits dictated by communication theory (estimates of achievable rates indicate up to Tbits/sec.),
3. to demonstrate interconnect design techniques for nano-signaling that can potentially approach the theoretical signaling limits
This is being made possible by a combination of several innovations that include (i) multi-wire (differential) full-duplex signaling, (ii) signal modulation, coding and equalization, and (iii) utilization, instead of avoiding, very-deep-submicron (VDSM) effects such as wave transmission for potential signaling.

0101254
Scott A. Hauk
University of Washington

CISE Research Infrastructure: An Infrastructure for Integrated Systems Education and Innovation

The research contained in this proposal represents a wide-ranging investigation into the future of single-chip systems. We will seek to develop a design methodology that can provide the benefits of multiple different resource types for numerous design domains. To support the design of such cutting-edge silicon systems, we will develop innovative techniques to handle numerous design issues. These will include investigations into the following critical issues in chip design: Development of techniques for integrating RF and Analog components into future 1V SoC designs. Creation of high-performance, power efficient digital logic families for supporting the stringent requirements of these systems. Investigation into reconfigurable subsystems for SoC designs, providing post-fabrication customization for support of multi-protocol and multi-algorithm systems. Integrated testing methodologies for complex, heterogeneous systems that can provide complete system test. Complete simulation and design methodologies that can handle complete system integration, architectural exploration, and validation. In addition to the development of new approaches to future chip design, we will also develop innovative techniques for educating future chip designers. By providing an integrated curriculum in VLSI/CAD, embedded systems, and complex system design, we will help create system architects capable of harnessing these radically new design techniques and opportunities. We will also seek to increase the opportunities in chip design for new constituents, especially under-represented groups to help increase the pipeline of new designers

The primary driver of the information revolution is advanced silicon processing. Consequently, system design is undergoing a fundamental change, moving from multiple chip solutions to system-on-a-chip (SOC) solutions. However, as was noted in the National Science Foundation's recent planning workshops on advanced VLSI systems, the testing and measurement thoery and practice related to these heterogeneous resources integrated into a SoC solution is a major unsolved problem that could greatly limit future advances.
The advancements in process technologies provide for radically new types of devices, with commensurate design challenges and test and measurement needs. An example of such a system currently under development at the UW is a human/machine transducer chip-Universal Transducer Chip, a single integrated system capable of providing a speech recognition interface to a ubiquitous wireless network. Such a system is likely to become the standard interface modality for a wide range of new applications, from smart homes and smart test benches to ubiquitous high-performance computing fabrics. However, to achieve this potential, there are multiple test and measurement issues that must be addressed:
o Radio frequency transceivers must be tested and characterized in the ISM (2.4GHz) and UNfl (5.6-5.8GHz) frequency bands for a broad range of emerging wireless standards
o Low power, high performance wireless hardware implementations must be tested and measurement techniques must be developed and validated for future SoC applications in the LMDS bands at 17GHz, and above
o Heterogeneous single-chip integration and test and measurement must be supported, allowing for the fabrication of RF, analog, high performance digital, and re-configurable subsystems within a single piece of silicon
The infrastructure contained in this proposal enables an investigation into the future of testing and measuring ultra-high-frequency SoC systems, years in advance of their commercialization. We will seek to develop and demonstrate a test and measurement methodology that can provide the benefits of multiple different resource types for numerous design domains. As an initial driver of these efforts, we will characterize a Human/Machine transducer chip, seeking to guide the development of future system-on-a-chip design and test methodologies. It is generally representative of future SoC systems that will operate at ever higher frequencies with ever-increasing levels of complexity. To support the design of such cutting-edge silicon systems, we will develop innovative techniques to handle numerous test issues:
o Validation of techniques for integrating RF and Analog components into future ultra-low-voltage SoC designs.
o Validation of high-performance, power efficient digital logic families for supporting these systems.
o Integrated testing methodologies for complex, heterogeneous systems that can provide complete system test through an optimum combination of on-chip and off-chip ultra-high-frequency test environments.
In addition to the development of new approaches for testing and measuring SoC chip designs, we will also develop innovative techniques for educating future high-frequency SoC designers. By providing an integrated curriculum including high-frequency test and measurement, along with a just-in-time learning environment, we will help create system architects capable of harnessing these radically new design techniques and opportunities.

Recent developments in mixed-signal systems, especially those integrating computing and
communication in a system-on-a-chip, have focused on the goal to communicate information via wireless devices and networks. While digital system design to process baseband information is moving into the low gigahertz (GHz) frequency range, the mixed-signal transceivers have to operate in the ISM bands (2.5 GHz up to 5.8 GHz) with even higher frequencies in the near future to satisfy bandwidth demands. Analog design advances have produced several transceiver designs up to 5 GHz, using CMOS, BiCMOS, and other technologies. To reduce noise, these designs tend to separate the transmitter and receiver, and so far, have provided only a single physical link (one transmitter and one receiver) in a wireless device. In the design area, this proposal addresses the creation and verification of scalable systematic design methods to integrate two or more physical links on one single chip to provide more bandwidth and flexibility in communication applications. A methodology to incorporate multi-links is scalable in the sense that more links can be added by application demands. To create this methodology, we propose the following design approaches:

1. Noise cancellation techniques and circuits to deal with digital switching noise.

2. Noise cancellation techniques and circuits to deal with RF noise interference between different transceiver links and circuits.

These circuits will be validated using case studies from industry with whom we have had close
collaborations: Texas Instruments, Motorola, and National Semiconductors, who will provide
advanced fabrication technologies and simulation models for this study.
The designs will be fully tested and the development of scalable test methods is the second focus of this proposal. Mixed-signal test advances, despite intense activities, have been rather slow, especially in high-frequency (GHz) test. We propose to investigate the following approaches and distill the results into a test methodology that can be scaled with respect to operating frequencies and process advances:

1. End-to-end digital test methods using one transmit link and one receive link on the same chip
to verify correct information transmission.

2. Designs of on-chip delay and phase measurement circuits, operating at the same frequency as
the transceivers.

3. Interface between ATE and on-chip test circuits to use test resources efficiently.
During the validation of these test methodologies, we will need access to advance test equipment for comparison purposes, and these equipment will be provided by our collaborator at Teradyne (Tualatin, OR) and Wavecrest (San Jose, CA).

Another level of integration involves the curriculum - research aspects of the proposed work,
which is being implemented in our current curriculum revision. Dissemination approaches re-used the distance learning methods and assessment supported by NSF, FIPSE, and our own
university. The proposal will deliver fundamental methodologies and techniques, and train the
first-generation system architects in high-frequency mixed-signal design and test.

This award provides funding for a three-year Combined Research-Curriculum Development (CRCD) program, entitled, "A Research-Based Electromagnetics-Circuits Curriculum for Giga-Scale Microelectronics," at the University of Washington, under the direction of Dr. Vikram Jandhyala. The overall objective of this project, which aims at a dramatic paradigm shift, is to combined electromagnetic (EM) and circuits principles in a unified, hierarchical manner in order to target high-technology areas.

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).

The objective of this research project is to advance the vision of a universal bio-signal acquisition system-on-chip (SoC). Such a system would have the ability to sense a wide variety of biological signals from the human body. The approach is to use a single reconfigurable ultra-low power low-noise amplifier and multi-rate, time-interleaved analog-to-digital converter (ADC) to support multi-channel, multi-type sensor data. This is in contrast to recent research on biological signal acquisition that focuses on custom integrated circuits that target a particular type of biological signal, such as an electrocardiogram (ECG) signal or an encephalogram (EEG) signal. Another goal is to include a low-power radio frequency (RF) transceiver on the SoC to transmit signal data and receive configuration information.

With respect to intellectual merit, the project has the potential to overcome technical challenges in the signal conditioning functional block for a bio-sensor SoC. The targeted signal versatility leads to a requirement for a very wide dynamic range for the amplifier front-end. The need to detect signals in very low signal-to-noise conditions also presents a circuit design challenge. Using CMOS to reduce cost prevents the use of some known techniques to address these challenges. The project investigates a reconfigurable low-noise amplifier for this purpose. The approach is multidisciplinary, integrating digital signal processing, analog and mixed-signal integrated circuit design, and medical science.

With respect to broader impacts, the proposed research has the potential to provide significant new capabilities for acquiring biological signals and to substantially lower the cost of such systems. If successful, this transformation could have significant impact on applications in diagnostic healthcare, home healthcare, personal fitness, and brain-controlled human-machine interfaces for prosthetic and other devices. One graduate student will be supported by the proposed project.