Sharad Malik - US grants

Malik This research is on verifying the temporal correctness of synchronous digital systems. The emphasis is on obtaining accurate, efficient algorithms within the paradigm of certified timing analysis. This combines the efficiency and coverage of timing analysis with the accuracy of timing simulation. Vectors that sensitize the long paths in the combinational parts of the circuit are generated by timing analysis. These are then used in timing simulation. The research addresses the problem that in order to provide these vectors, timing analysis must consider the functionality of the circuit components.

EIA-9911078
Margaret Martonosi
Princeton University

CISE Research Instrumentation: Instrumentation Support for System-On-A-Chip and Embedded System Research

The Department of Electrical Engineering at Princeton University will purchase a high-end server, workstations, networking hardware, and CAD tools, which will be dedicated to support research in computer engineering. The equipment will be used for several research projects, all generally in the areas of Computer Architecture, Computer-Aided Design, and particularly focused on advancing design and architecture techniques for embedded systems and systems-on-a chip.

In a fundamental paradigm shift system design in the semiconductor industry, entire systems are being built on a single chip, using multiple embedded functional blocks called cores. This has been made possible by the ever-increasing density of chips. The current 0.25-micron technology has made it possible to integrate tens of millions of transistors on one chip, and considerable interest is focused on discussing what the contents of billion-transistor systems-on- a-chip (SOCs) ought to be.

We propose to develop algorithms and tools to provide key technologies with breakthrough potential to semiconductor companies,and to develop efficient software environments and tools to deal with all aspects of the SOC design problem.

Given slowdowns in semiconductor technology scaling, it has become increasingly challenging to maintain processor performance scaling at acceptable power constraints. In response, microprocessors increasingly use complex architectures with heterogeneous parallelism and specialized compute units known as accelerators. Accelerators provide high compute performance at reduced power/energy by avoiding the overhead of instruction-programmability. The key challenge, however, is that unlike traditional microprocessor CPUs, accelerators have no durable, portable instruction set architecture (ISA), and instead are programmed via drivers or library APIs. These increase the effort of porting accelerator-oriented programs to other platforms with similar functionality but different implementations. The increased effort has serious consequences for software cost. Furthermore, the fact that accelerators have no formal, durable ISA causes increased verification complexity at a time when it is already the limiting factor in the design of future computing platforms. The intellectual merits of this work are that the research is developing Instruction-Level Abstractions (ILAs) that extend the ISA concept to accelerators in order to address these programming and verification challenges. ILAs offer a formal and high-level summary of the visible state updates that an accelerator will perform on each invocation. The project?s broader significance and importance are the work?s ability to impact industry designs of future accelerator-based computing platforms and thereby help sustain the US computing industry.

There are two components to an ILA: specifying the state updates, and specifying the Memory Consistency Model, i.e., the permitted ordering of state updates relative to other parallel compute elements. The research develops ILA methodologies that are (i) uniform across accelerators, (ii) symmetric with the ISA of instruction-programmable processors and (iii) unified across both computation (state change) and memory (data/storage state update) abstractions. To show the value of ILAs, the research develops: (i) ILA specification mechanisms for a rich set of accelerators, (ii) synthesis techniques and tools for generating these ILAs automatically, (iii) verification techniques and tools that check these abstractions against implementations and (iv) further tools enabled by ILAs including full-system architectural simulation. Through these efforts, this work addresses fundamental software portability and verification gaps in the design and deployment of accelerator-oriented systems.