1975 — 1983 |
Breuer, Melvin Hayes, John (co-PI) [⬀] |
N/AActivity Code Description: No activity code was retrieved: click on the grant title for more information |
Design Automation of Digital Systems @ University of Southern California |
0.915 |
1979 — 1984 |
Breuer, Melvin |
N/AActivity Code Description: No activity code was retrieved: click on the grant title for more information |
Testing Methodologies For Complex Digital Systems @ University of Southern California |
0.915 |
1981 — 1982 |
Parker, Alice (co-PI) [⬀] Breuer, Melvin |
N/AActivity Code Description: No activity code was retrieved: click on the grant title for more information |
Computer Science and Computer Engineering Research Equipment @ University of Southern California |
0.915 |
1983 — 1987 |
Parker, Alice (co-PI) [⬀] Breuer, Melvin |
N/AActivity Code Description: No activity code was retrieved: click on the grant title for more information |
The Adam (Advanced Design Automation System) Vlsi (Very Large Scale Integrated) Design System @ University of Southern California |
0.915 |
2004 — 2009 |
Chugg, Keith (co-PI) [⬀] Gupta, Sandeep [⬀] Ortega, Antonio (co-PI) [⬀] Breuer, Melvin |
N/AActivity Code Description: No activity code was retrieved: click on the grant title for more information |
Itr-(Ase+Nhs)-(Int): a Digital System Paradigm For Yield Enhancement and Graceful Degradation Via Error Acceptance @ University of Southern California
Abstract ITR-(ASE+NHS)-(int): A Digital System Paradigm For Yield Enhancement and Graceful Degradation Via Error Acceptance
Despite extensive research into improving fabrication processes, continued VLSI scaling will be inhibited by high variations in process parameters, higher defect densities, and higher susceptibility to external noise. We propose two notions, namely error-tolerance and acceptable operation, to facilitate imprecise computation: these notions systematically capture the fact that an increasingly large class of digital systems can be useful even if they do not perfectly conform to a rigid design specification. We propose to develop a systematic methodology for design and test of this class of digital systems that will exploit the notion of error tolerance, to enable dramatic improvements in scale, speed, and cost. In the proposed methodology, system specification will include a description of the types of errors at system outputs, and the thresholds on their severities, that are tolerable. The design methodology will exploit this information to obtain designs that provide higher performance and/or lower costs.
Over the next 15 years, the proposed approach will provide dramatic improvements in scale, speed, and cost for a wide class of digital systems, including many integral to NHS. This will enable development and wider deployment of devices with advanced capabilities in areas such as speech processing, real-time translation of spoken natural languages, and biometrics.
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0.915 |
2007 — 2011 |
Breuer, Melvin Gupta, Sandeep (co-PI) [⬀] |
N/AActivity Code Description: No activity code was retrieved: click on the grant title for more information |
Csr---Sma: a Cad Framework to Support the Effective Application of Redundancy At the Switch/Architectural Level For Future Technologies Having High Defect Rates and Variations @ University of Southern California
Computer-aided-design systems for digital circuits interfaces with computing technologies and fabrication processes that exhibit high levels of variations, defect densities and noise susceptibility. A direct extrapolation and ad-hoc application of existing defect-tolerance (DT) and fault-tolerance (FT) techniques erodes much of the benefits of new technologies. The objective of this research is to develop a systematic framework for design and test of digital systems that optimizes a specified combination of cost, performance and power for nanometer technologies.
A framework for efficient application of existing and new DT and FT techniques, including the use of spares, task rescheduling, coding and DFM rules is being developed. This framework works in conjunction with existing design flows and includes components spanning the levels of technology (variations/defects), layout, circuit, logic, architecture and system. Key innovations are embodied in new techniques for identifying efficient ways of assigning spares, reconfiguring around faulty modules, and modifying selected parts of a module to improve yield. To obtain optimality, a design explorer is being developed to efficiently search the space of alternative designs. This research will provide the first framework for design of digital systems for the remaining years of CMOS scaling and beyond. We will train graduate and undergraduate students in this methodology of the future and share our results with academic and industrial colleagues.
This research will provide immense benefits to society by being a key enabler of an era of inexpensive and powerful digital devices with significant educational, health and security functions.
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0.915 |
2010 — 2014 |
Breuer, Melvin Gupta, Sandeep (co-PI) [⬀] |
N/AActivity Code Description: No activity code was retrieved: click on the grant title for more information |
Shf: Small: a Digital System Paradigm For Yield and Robustness Enhancement Via Global Analysis and Compensation @ University of Southern California
Adoption of each new generation of nano-scale technology is accompanied by lower yields, stagnant performance or increasing chip-to-chip performance variability, and decreasing robustness to environmental stress. The objective of this research is to identify new avenues for design, analysis, and testing to help compensate for these trends. This research takes a global view of the role of a module in the overall system architecture. This research will focus on two specific issues, namely (1) the impact of a fault in a module on the overall system operation and performance, and (2) the ability to reconfigure one module to compensate for a fault in another module by preventing it from affecting the correct operation of any system or user task. Additional case studies will be conducted to further demonstrate that both these aspects of a global view significantly improve system yield and performance. A systematic approach will be developed to exploit such a global view to dramatically improve yield, performance, and robustness. A completely new framework ? models, information, analysis, and algorithms ? for assembling systems using faulty (and fault-free) components ? will also be developed.
The utilitarian gains to society of this project are likely to be substantial. First, without changing any existing design, the proposed analysis and test approaches will provide significant improvements in yield, performance, and robustness to soft-errors. Second, the proposed analysis, design, test, and global compensation techniques will also help improve yields. Since the types of systems where this research is directly applicable include high-performance processors, the benefits provided will be amplified by the high price such processors fetch and the high volumes in which they are manufactured. Furthermore, since this research is orthogonal to much of the on-going research for improving yield and performance, improvements it provides can be combined with those provided by other approaches. Finally, this project will provide unique educational and training opportunities, for USC students as well as working professionals in the field.
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0.915 |
2016 — 2019 |
Beerel, Peter [⬀] Breuer, Melvin |
N/AActivity Code Description: No activity code was retrieved: click on the grant title for more information |
Shf: Small: Methodology, Tools, and Circuits For Bundled-Data Resilient Asynchronous Design @ University of Southern California
The impact of this research will span both academia and industry, yielding: (1) fundamental theory to design and analyze asynchronous circuits that gracefully adapt to process variability and makes near-threshold (i.e., low-power) computing practical; (2) a CAD flow that makes asynchronous circuits far more attractive for the ultra-low-power market. The research is coupled with a comprehensive plan to foster innovation in engineering, including plans for commercializing this research. The plans also include student training and future workforce development for the electronic chip industry.
The unrelenting demand for longer battery life and energy-efficient designs is increasing the desire for integrated chip voltage supplies to go lower and lower, approaching near threshold levels. This aggravates process variability which forces increasing margins in traditional synchronous clock periods, yielding far-from-optimal solutions. The focus of this proposal is a recently proposed new resilient asynchronous design style, called the "Blade", that is robust to meta-stability, robust to hold times, and architecturally agnostic, not relying on architectural replay to correct for errors. This proposal will create a comprehensive framework to support the efficient design of Blade circuits with emphasis on test, synthesis, and physical design.
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0.915 |