Massoud Pedram - US grants

This research is on finding efficient techniques for producing solutions to logic synthesis and physical design problems both simultaneously and interactively. Two problem areas are being investigated: integrating logic synthesis with physical design; and layout algorithms for Boolean networks. In the first area, a prototype synthesis system which is capable of making synthesis decisions based on both logic level information and detailed data about the interconnecting wires and characteristics of the physical media is being developed. The key idea is to generate a placement of the Boolean network that captures the structure of the layout. The correspondence between logic and layout representations is maintained during iterations. Both technology independent and technology dependent logic transformations are accommodated. In the second area, ways to assign the I/O pads or place the nodes of an unmapped Boolean network, where the nodes still have technology independent logic realizations, are being investigated. Physical design tools which effectively capture the structural characteristics of Boolean networks and can handle nodes of inexact or approximate area, intrinsic delay and drive are being developed. Accurate and efficient modeling of interconnect during logic synthesis and layout plays a key role in the algorithm development.

Dubois A testbed for experimenting with memory hierarchies in multiprocessors is being supported. A processor node in the testbed contains cache and memory system controllers made from field-programmable gate arrays. To experiment with a memory control mechanism or coherency technique, the investigators program the gate arrays to implement the mechanism. For software support of experimental techniques, the GNU-C compiler is being modified to generate appropriate code, such as non-blocking prefetches, and the Mach microkernel is being ported to provide thread scheduling.

This research investigates modeling and estimation of power consumption as well as techniques for minimizing power at the various levels of design abstraction (layout, logic, register- transfer and behavioral levels). Principles and methods to guide the design of power efficient electronic systems are being explored; and the impact of availability of low-power design techniques on chip, module, and system level designs is being assessed. Topics being investigated include: spatio-temporal power estimation; state assignment for low power; power dissipation in boolean networks; common subexpression extraction; and FPGA synthesis for low power.

The research project is on power modeling, analysis and minimization for battery-powered digital CMOS circuits. An integrated battery-hardware model of the battery-operated circuits is being developed. It accounts for architectural and gate-level features of the circuit, statistical properties of the instructions and data that are applied to the circuit, and electro-chemical and output characteristics of the battery cell that powers the circuit. Using this unified model, the project is addressing the problem of finding appropriate metrics and effective design practices to maximize the battery service life under a performance constraint. Algorithms and techniques are being developed for: (1) static and dynamic voltage scaling, selection of battery cells to match a given circuit, (2) RT-level design of low power VLSI circuits to match a given battery cell, (3) use of multiple battery cell types within a battery pack to maximize the battery service life for given form factor and weight, and (4) dynamic power management. Powerful mathematical models and algorithms for power estimation and management in complex battery-powered digital CMOS designs are being explored.

This project investigates the problem of simultaneous scheduling and HW/SW mapping of the computational and communication processes in a generalized task flow graph so as to minimize the energy dissipation of the target system while satisfying a given deadline. This project also studies a number of problems related to power analysis and optimization at the behavioral and RT levels, including power modeling and characterization of Intellectual Property cores, and automatic clock gating. Finally, the project develops dynamic power management algorithms, which save power by shutting down idle devices or slowing down underutilized devices, and develops optimal policies for operating system (OS) directed power management and dynamic voltage and frequency scaling under a variety of system models

One of the key problems confronting computer system designers is the management and conservation of energy sources. This challenge is evident in a number of ways. The goal may be to extend the battery lifetime in a computer system comprising of a processor and a number of memory modules, I/O cores, and bridges. This is especially important in light of the fact that power consumption in a typical portable electronic system is increasing rapidly whereas the gravimetric energy density of its battery source is improving at a much slower pace. Other goals may be to limit the cooling requirements of a computer system or to reduce the financial burden of operating a large computing facility. The objective of this research is to develop system-wide power optimization algorithms and techniques that eliminate waste or overhead and allow energy-efficient use of the various memory and I/O devices while meeting an overall performance requirement. More precisely, this project tackles two related problems: dynamic voltage and frequency scaling targeting the minimization of the total system energy dissipation and global power management in a system comprising of modules that are potentially managed by their own local power management policies, yet must closely interact with one another in order to yield maximum system-wide energy efficiency. The broader impacts of this project include the development of energy-aware computer systems as the key for cost-effective realization of a large number of high-performance applications running on battery-powered portable platforms and the education and training of young researchers and engineers to be able to address complex and intertwined energy efficiency/performance challenges that arise in the context of designing next-generation information technology products and services.

Current-day electronic computers are not fundamentally different from purely mechanical computers: the operation of either can be described fully in terms of classical physics. By contrast, computers could in principle be built to profit from actual quantum phenomena that have no classical analogue, such as entanglement and interference, sometimes providing exponential speed-up compared with classical computers. Every quantum algorithm requires the implementation of a quantum oracle (logic circuit), whose function is to recognize solutions to a given problem. To completely exploit the "quantum parallelism," this oracle should be realized by using quantum gates because it must be able to handle an arbitrary superposition of basis vectors (quantum states.) A key problem is thus how to construct a minimum-cost realization of this kind of quantum logic circuit. This research focuses on the development of an efficient synthesis framework for quantum logic circuits. The proposed synthesis algorithm and flow can generate a quantum circuit using the most basic quantum operators, i.e., the rotation and controlled-rotation primitives in the Bloch Sphere Representation. More importantly, this work introduces the notion of quantum factored forms, and develops a canonical and concise representation of quantum logic circuits, called a quantum decision diagram (QDD). The QDDs are amenable to efficient manipulation and optimization including recursive unitary functional bidecomposition. Subsequently, an effective QDD-based algorithm is developed and applied to automatic synthesis of quantum logic circuits. If successful, this research will pave the way toward building quantum computing circuits and eventually systems. Its impacts can thus be broad and substantial.

Peak power dissipation and the resulting temperature rise have become the dominant limiting factors to processor performance and a significant component of its design cost. Expensive packaging and heat removal solutions are needed to achieve acceptable substrate and interconnect temperatures in high-performance microprocessors. Current thermal solutions are designed to limit the peak processor power dissipation to ensure its reliable operation under worst-case scenarios. However, the peak power and ensuing peak temperature are hardly ever observed. Dynamic thermal management (DTM) has been proposed as a class of micro-architectural solutions and software strategies to achieve the highest processor performance under a peak temperature limit. When the chip approaches its thermal limit, a DTM controller initiates hardware reconfiguration, slow-down, or shutdown to lower the chip temperature. Possible response mechanisms include micro-architectural adaptations e.g., fetch toggling, register file resizing, and issue width reduction, and/or on-the-fly performance adjustment e.g., dynamic voltage and frequency scaling and functional unit shut-down. The proposed research aims to develop a new DTM solution that takes a global, predictive approach based on constructing and utilizing a continuous-time Markovian decision process model of the microprocessor chip and the application programs. The offline algorithms developed in this framework are provably optimal whereas the online versions of these algorithms are easily deployable and highly flexible. The project thus produces temperature-aware policies and techniques for ensuring that the microprocessor chips operate within the allowed temperature zone, having maximum possible performance yet not being over-designed.

0541469
Massoud Pedram
U of Southern California

Hardware/Software Support and Algorithms for Dynamic Backlight Scaling in TFT LCDs

Display components have become a key focus of efforts for maximization of the battery lifetime in a wide range of portable, display-equipped, microelectronic systems and products. A particularly effective technique in reducing the power consumption of all kinds of displays is the dynamic backlight scaling technique, where the intensity of the backlight lamp and the LCD transmittance function are changed concurrently and in proportion so that the same visual perception is created in the human eyes at much lower levels of power consumption. This research therefore aims to develop spatiotemporal and/or color-aware backlight scaling techniques for pixel transformation of the displayed still images or video streams so as to maximize the energy saving in a target platform. The new techniques , which take advantage of the human visual system characteristics to minimize distortion between the original and backlight-scaled images/videos, will be implemented and demonstrated on the Apollo Testbed II hardware platform. The broader impact of the research is to significantly reduce the power consumption of typical handheld devices, increasing their discharge-cycle lifetime, thereby, enabling more widespread and convenient use of such devices. The backlight dimming technology can also be applied in AC-powered systems where the key concern is the energy cost to the individual user as well as the society at large. This technology has the potential to reduce the typical energy bill of a desktop computer by 30% or so (when the system is being used). This research, if successful, will expedite introduction of advanced display technologies (such as LED-based backlighting for LCDs, or organic LED-based displays) since it will reduce their power cost without sacrificing quality.

PI: Pedram, Massoud
Proposal No: 0811876
Title: CPA-DA: Design Techniques and Tools to Enable and Enhance Coarse-Grain Power Gating in ASIC Designs
Institution: University of Southern California


This project focuses on coarse-grain power gating in ASIC designs, which switches entire blocks/rows of standard cells. This choice is due to lower cost and greater leakage savings of coarse-grain power gating compared to its fine-grain counterpart, which inserts the header or footer in each standard cell in the ASIC design library. The project results are expected to include the following: (i) Distributed sleep transistor placement and sizing; (ii) Sleep signal scheduling to minimize the peak current demand on wakeup; (iii) Mode transition energy minimization to enable more frequent mode transitions; (iv) Local sleep signal generation for autonomous power gating; and (v) Power gating to enable multiple power modes. This proposal aims to address each of these tasks by developing algorithmic or mathematical programming solutions to solving each step and by developing a design flow and prototype software tools that enable widespread adoption of this very interesting and important technology in the ASIC design.

The semiconductor industry?s $261 B in 2006 revenue does not accurately reflect its crucial role in enabling a $47 T ($61 T on a PPP basis) world economy to thrive and grow. This industry underpins the systems and technologies on which the people and governments of the world rely on for future prosperity. This industry is currently facing some extraordinary challenges, including variability of nano devices as well as excessive power dissipation in circuits and systems. In order for the industry to continue to expand and prosper, it is critical to address these challenges heads on. The proposed research takes on one of these two fundamental challenges, i.e., the ?power crisis?. The decisive impact of the proposed research will be the enablement of the CMOS scaling to continue unabated for the next 10-15 years. Moreover, the project will actively engage students both at graduate and undergraduate levels. For graduate students, active participation in the research work will enhance their creative and multidisciplinary thinking and prepare them for future independent work. The PI?s commitment of involving undergraduate students in carefully designed projects will help foster their long lasting enthusiasm in scientific research activities. Integration of research into curriculum development and classroom teaching will provide a powerful venue for the dissemination of research results that greatly compliments the traditional venues of conferences and archival journals.

With the increasing levels of variability in the characteristics of nanoscale CMOS devices and VLSI interconnects and continued uncertainty in the operating conditions of VLSI circuits, achieving power efficiency and high performance in electronic systems under process, voltage, and temperature variations as well as current stress, device aging, and interconnect wear-out phenomena has become a daunting, yet vital, task. This proposal tackles the problem of system-level dynamic power management (DPM) in systems which are manufactured in nanoscale CMOS technologies and are operated under widely varying conditions over the lifetime of the system. Such systems are greatly affected by increasing levels of process variations typically materializing as intrinsic (random) or systematic sources of variability and wearout/aging effects in device and interconnect characteristics, and widely varying workloads and temperature fluctuations usually appearing as sources of uncertainty. At the system level this variability and uncertainty is beginning to undermine the effectiveness of traditional DPM approaches. It is thus critically important that we develop the mathematical basis and practical applications of a variability-aware, uncertainty-reducing DPM approach with the following unique features and capabilities: Utilization of a two-tier stochastic modeling framework based on the theories of variability-sensitive, partially observable Markovian Decision Model and closed-loop feedback control theory, which can efficiently cope with variability and effectively reduce uncertainty in key system parameters. The framework also allows for self-learning (adaptive) policy optimization approaches, and multi-manager systems with multiple reward and cost rates for simultaneous optimization of the system energy consumption and performance.

Successfully overcoming the challenges addressed by this project will result in significant energy savings for a typical server. Other impacts of this research includes the development of a new and powerful mathematical framework for resource management in complex and large systems that can deal with multiple-agents, multiple reward and cost rates and discount factors while accounting for effects of variability and simultaneously reducing the impact of uncertainty through measurements and sampling. The stochastic decision making framework with closed loop feedback control is also useful for solving a variety of other problems including dynamic thermal control, concurrent DPM and task scheduling in multi-core processor systems, consideration of total system?s energy efficiency, energy-efficient power delivery network design. If successful, the approach can result in a practical stochastic optimization framework for handling many important problems, ranging from energy efficiency improvement (and hence reduction in cost of operation) for electronics systems to data centers comprised of a large number of server/storage elements. Education, Outreach, and Training Programs include new curricula; recruiting under-represented students; research internship opportunities for undergraduates; and a Junior Scholars program for high school students.

High cost differentials are causing many steps of IC manufacturing to increasingly move overseas. This project considers the problem of evaluating trustworthiness of digital ICs fabricated by untrusted vendors who may insert hardware Trojans. The proposed EDICT framework (Evaluation and Design of IC's for Trustworthiness) tackles two main challenges, namely the unavailability of a gold-standard chip combined with high process variations, and the fact that Trojans are introduced by intelligent adversaries. EDICT exploits the key difference between the impact on circuit parameters of Trojans and process variations - universal shift vs. random - to detect Trojans, including those causing deviations smaller than process variations. In particular, this project is developing new techniques to identify effective measurements - sequences of values applied at IC inputs and parameters measured - for evaluation of chip's trustworthiness.
This project represents a radical extension of techniques for generating vectors for high-volume-manufacturing testing by focusing on new targets that capture all possible Trojans, developing the first suite of techniques to characterize and identify Trojans in a non-destructive manner, and developing the first methods to identify additional unauthorized functionality.
By providing the technical infrastructure to evaluate trustworthiness of ICs, this project enables defense and civilian sectors to exploit global semiconductor industry at reduced risk. Trustworthy digital systems bring many benefits to society. They improve many essential services - health, security, education, etc. - and bring lower costs. Finally, this project trains graduate students in developing, and defense and industry experts in using, new approaches and tools for evaluating IC trustworthiness.

This is a proposal to hold an NSF CISE-sponsored workshop in to survey the state-of-the art in cross-layer power optimization and management, to identify areas that require further research and development, and to chart a transformative research agenda for this field. The workshop is expected to bring together about 50 of the leading researchers studying system-wide power optimization techniques and dynamic power management from both academe and industry including representatives from major chip design companies. All of the material from the workshop will be made available to the research community and a detailed report will be prepared and submitted to NSF.

Power efficiency is an important driver for the semiconductor industry and all of its components. By investigating the shortcomings and weaknesses of the current approaches to power and/or energy efficiency it is expected that a new slate of low power technology and circuit solutions with tangible impact on the design of the next generation portable electronics as well as high performance (yet energy aware) computing will be achieved.

Mobile devices such as smartphones and tablets are intended for usage under demanding physical conditions. As a result, their displays face two unique challenges. First, contextual factors, including the viewing angle, ambient lighting, and unwanted shaking of the device, tend to distort the perceived display content. Moreover, the display is known to be among the largest power consumers on a state-of-the-art mobile device. The goal of this project is to provide the algorithmic foundation as well as software and hardware solutions required for addressing these two challenges. As a close collaboration between Rice University and the University of Southern California, the project targets the following scientific contributions. (1) Sensor-based inference of viewing context that efficiently obtains the viewing context from sensors available in modern mobile devices. (2) Compensation for contextual factors that transforms the display content to produce an improved user perception in terms of fidelity and/or usability. (3) Supply voltage scaling and color/image transformations that modify the display data to significantly reduce the power consumption of mobile OLED displays under human perceptual constraints.
By improving the performance and energy efficiency of mobile displays under challenging viewing conditions, this project will extend the reach of mobile computing beyond its current levels, therefore, having a far-reaching socio-economic impact. Through the NSF/FDA Scholar-in-Residence (SIR) program, graduate students working on this project will visit the US FDA and collaborate with FDA researchers to apply research results to medical imaging problems with mobile displays. The multidisciplinary nature of the proposed research will invite new research problems in system architecture and circuit design, human-computer interaction, image processing, and photometry. It will also provide a multidisciplinary platform for undergraduate and graduate education and research.

This proposal provides a systematic approach to combining existing electrical energy storage technologies and power conversion circuit designs with sophisticated runtime management policies to create a hybrid electrical energy storage (HEES) system with performance metrics that would be superior to those for any of its constituent components. In particular, the proposed research focuses on: (i) Architecture design and charge management, including charge allocation, migration, and replacement policies in HEES systems; (ii) Application driver and customization, including application to portable systems, and (iii) System prototyping and evaluation, including HEES system deployment studies.

This research claims to produce unprecedented benefits in terms of energy availability and efficiency in electronic systems as well as significant reductions in cost of operating these systems. In particular, the proposed work aims to achieve 2x cost reduction and 10x cycle life improvement over conventional electrical energy storage systems. This will in turn enable the design of integrated products and platforms that deliver a wide range of new capabilities based on efficient power delivery and local energy storage. Another expected benefit of this proposal is the training of students, who will acquire knowledge in the development of new means and methods for electrical energy storage, conversion and delivery.

Recent studies emphasize the importance of energy-efficient computing for sustaining advancements in information technology and addressing critical societal challenges. The exploration of holistic power optimization and management solutions that cut across multiple layers of the computing stack and infrastructure to be studied in this project will better enable available opportunities for maximizing energy efficiency. The research will advance the state-of-the art in sub-10nm device design, modeling, and optimization, standard cell library design and characterization, circuit speed vs. energy efficiency vs. reliability trade space exploration, and heterogeneity modeling at the chip level. The challenges and opportunities in this research will provide directions for developing many of the technologies and approaches that are needed to design energy-efficient computing systems of the future and ensure sustainability of the information technology ecosystem. Education, outreach, and training programs enhanced by this project will include development of new educational modules, recruitment of minority and under-represented students, as well as undergraduate learning and research internship opportunities for undergraduates.

From a technical standpoint, this project will innovate at two cross-layer boundaries: (i) Technology and Circuits, and (ii) Circuits and Architectures. More precisely, a first thrust of the research will focus on developing deeply-scaled (multi-gate) CMOS devices and logic cell libraries that offer high energy efficiency, fast switching speed, and reliability. A second thrust targets the design of low dynamic and standby power circuits, circuit designs capable of robust and energy-delay optimal operation in multiple voltage regimes, and means for effective chip-level power management. To accomplish these research objectives, analysis and simulation tools will be developed to characterize properties such as Ion/Ioff ratio, energy efficiency, and variation tolerance of the deeply-scaled (e.g., sub-10nm) FinFET devices. In addition, questions of how the new devices can be used for designing memory and logic cells that can seamlessly operate at low (near-threshold) and high (super-threshold) supply voltages will be explored. Finally, key challenges in modeling, deployment, and reconfiguration of circuit fabrics and architectural templates to improve the overall energy efficiency of system-on-chip designs will be addressed.

Advances in "beyond-CMOS" device technologies and corresponding logic families are now seen as a key step towards achieving the next major leap in high-performance computing. The research challenges and opportunities described in this research provide directions for developing many aspects of a very promising "beyond-CMOS" technology, which can result in extremely high performance, yet energy-efficient, computing system, and thereby, ensure sustainability of the information technology ecosystem. Education, Outreach, and Training Programs include development of new educational modules; recruitment of minority and under-represented students; as well as undergraduate learning and research internship opportunities for undergraduates.

The technical goal of this project is to investigate the state-of-the-art in design and optimization of superconducting DC-powered single flux quantum (SFQ) logic circuits and draw up a comprehensive research plan for developing a standard cell-based design methodology and supporting computer-aided design tools for the SFQ logic at the register-transfer-level. In the process, this project will analyze similarities and differences between the SFQ logic and standard digital CMOS logic fabrics, investigate various problems related to the synthesis, optimization and physical design of SFQ logic gates and circuits, and finally produce a number of computer-aided design techniques and prototype software tools for proof-of-concept demonstrations, including a standard cell characterization tool, a static timing and power analysis tool, a frontend logic synthesis, and a backend placement and clock network design tool. In short, this research aims to achieve major strides in the development of advanced design automation technologies in support of large-scale superconductive SFQ digital electronics to meet the needs of future energy-efficient, high-performance exa-scale computing systems.

Deep neural networks (DNNs) have been employed in wide application domains thanks to their extraordinary performance. Hardware implementations of DNNs are of critical importance for the ubiquitous embedded and Internet of Things (IoT) devices, which call for high performance in energy and resource constrained systems. This project aims to address the challenges when mapping complicated DNN models into hardware for energy-efficient and performance-driven implementations. The proposed techniques will promote wider adoptions of deep learning into both high-performance and low-power computing systems. The project will also enhance economic opportunities and have significant societal benefits via solutions that support broader adoption of intelligent systems for big data analytics, weather modeling and forecasting, disease diagnosis and drug delivery, and medical image processing. The research advances will be incorporated into coursework taught by the investigators. Activities on engaging underrepresented, undergraduate, and K12 students will be designed in collaboration with the Northeastern University Center of STEM Education and University of Southern California's Viterbi Center for Engineering Diversity. All software code from the project will be released via GitHub and educational modules and tutorials will be make available to the research community, industry, and government.

Exploring the inherent model redundancy of DNNs, this project will develop an algorithm-hardware co-optimization framework for greatly reducing DNN computation and storage requirements by leveraging ADMM (alternating direction method of multipliers), a powerful optimization technique. This project first solves the challenge in the application of ADMM due to the non-convex objective function in DNN training, and thereby lack of guarantees on solution feasibility, solution quality, and low runtime. Therefore, an integrated framework of ADMM regularization and masked mapping and retraining will be developed and further improvements on solution quality, performance-driven computation/storage reduction, and hardware feasibility will be investigated. Next, the project proposes a unified weight and intermediate result pruning and quantization technique that explores all four redundancy sources of DNN models. Due to the impact on energy efficiency of hardware implementations of DNNs, nearly all DNN models, or at least the most computationally intensive convolutional layers can be then placed on a single chip. Finally, design-time parameterization and algorithm-hardware co-design solutions will be developed for efficient utilization of available hardware resources, achieving high performance, energy efficiency, and adaptation capability. Extensive experimentation and evaluation will be performed to validate and tune the proposed technique with prototype systems using FPGA devices.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

The critical dependence of the world economy on energy-efficient operations in computing are now almost universally recognized. To this end, advances in ?beyond-CMOS? device technologies and corresponding logic families are now seen as a key step towards achieving the next major leap in high-performance computing. The challenges and opportunities described in this research provide directions for developing many aspects of a very promising ?beyond-CMOS? technology, which can result in extremely high-performance, yet energy-efficient, computing systems, and thereby ensure sustainability of the information-technology ecosystem. SuperConductive Electronics (SCE) based on the Josephson junction (JJ) Single Flux Quantum (SFQ) logic cells have evolved into a within-reach ?beyond-CMOS? technology, with switching speeds in the hundreds of GHz and energy dissipation of 10^-19 or less Joules per transition. The project will enhance business and societal opportunities by producing ultra-high performance and energy-efficient electronics for a wide range of computing fabrics, and in the process will also contribute to enhancing the technological capabilities of the US by providing education and research opportunities to undergraduate, graduate, and underrepresented students by including them in the planned research.


This research aims to achieve major strides in the development of advanced circuits, architectures and design-automation technologies in support of large-scale superconductive SFQ digital electronics to meet the needs of future energy-efficient, high-performance exa-scale computing systems. Research on design automation will enable large-scale SCE systems integration. Targeting both DC-powered energy-efficient Rapid SFQ and AC-powered Adiabatic Quantum-Flux-Parametron circuit families, this research aims to solve four key problems associated with the design automation and optimization of SFQ logic circuits, namely: minimization of SFQ circuit retiming to the number of buffers for operating frequency improvement and/or clock-phase consistency; path-balancing technology mapping for sequential SFQ circuits with loops; timing-driven global placement using unique features of SFQ logic families and a powerful mathematical optimization tool; and circuit partitioning to enable effective current recycling.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

The advancement of computing remains focused on ever increasing performance. While energy has become a metric of interest for mitigating thermal issues or increasing battery life of mobile devices, energy efficiency has largely neglected sustainability and in particular, computing's impact on the environment and energy resources of the planet. For example, while embodied environmental costs (e.g., carbon emissions) of integrated-circuit (IC) manufacturing often exceed its operational carbon footprint, this is relatively unknown or the reverse is presumed to be true in the computing community. Furthermore, the use of rare metals such as tantalum, tungsten, and gold, in electronic equipment contribute to the inevitable exhaustion of the planet's resources. There is an urgent need to consider factors beyond operational-phase energy consumption of the computing infrastructure to truly combat carbon and other harmful emissions present during the full computing lifecycle to combat the existential threat of climate change.

This project proposes a series of community oriented activities culminating in a workshop to both increase awareness among researchers in the domain of computing about these factors of sustainable computing and to specify the challenges and potential possible solutions to achieve sustainable computing including, but also beyond the operational phase of the computing technology. A particular goal will be to facilitate cross pollination of ideas among researchers across different disciplines encompassing not only computing sciences but also, environmental sciences and political sciences to identify sustainable methodologies for design and operation of computing infrastructure. The novelty and intellectual merit of this project is in identifying gaps in knowledge that need to be bridged to truly make computers sustainable. In particular, this project will start with a series of invited talks from experts from diverse fields with deep insights on these aspects that ultimately affect the sustainability of computing resources targeted at computing researchers. These talks will be delivered remotely with an online platform. Following these enlightening talks, this project will host an in-person workshop bringing computing researchers together to discuss the lessons learned from the talks and how these ideas can be incorporated in various types of computing devices from low power miniature systems such as Internet-of-Things (IoT) devices to warehouse-scale computers such as data centers. Through this activities, the intention is to create awareness and strategies to create a sustainable future for computing systems.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.