Alexander A. Sawchuk - US grants

The Principal Investigators will design and experimentally demonstrate a sophisticated and novel photonic interconnection network that interconnects 2-D arrays of optical inputs and outputs. The network is a general volume (bulk) multistage shuffle exchange design using high efficiency fixed optical interconnections along with optoelectronic integrated circuits (OEICs) to provide dynamic routing and signal regeneration. The OEICs are designed specifically to attain the performance necessary to carry data at high bandwidths (> 100 MHz). The routing of signals is determined by the polarization encoded on the light beam on which the data signal or optical power is carried. Furthermore, the circuits are optimized to allow for a high density of similar switches arranged in a 2D array format. For this reason, the OEICs will be fabricated using Ino.53GaO.47As which has been found by the PIs to be compatible with very low power dissipation circuits, hence lending itself to high array circuit densities. Another feature of the system under investigation is that it will be optically (rather than electrically) powered using integrated InP photovoltaic cells for the array elements. Optical powering has the advantages of supplying power with a low level of electrical cross-talk between array elements, and is relatively easily distributed in high density networks where interconnection to remote pixels can be a significant problem. The program involves a close collaboration between two groups at USC -- one whose expertise has been demonstrated in the field of interconnection architecture design, and the other which specializes in the design and fabrication of OEICs in InP-based materials. The combination of disciplines necessary for the successful completion of the project goals will lead to significant advances in the state- of-the-art of photonic interconnection networks. Furthermore, this program is to be complemented by a partnership with photonics industry, enhancing our ability to eventually realize commercial photonic switching networks using advanced device technologies such as those proposed here.

9422106 Leahy This award is to purchase equipment dedicated to research in computer and information science and engineering. Specifically, the equipment will be used for research in multi-dimensional signal and image processing, including in particular: 1) fusion of multimodal neuroimaging data; 2) adaptive quantization of image and video; 3) automatic target recognition via deformable template matching; 4) design of high resolution diffractive optics for photonic interconnections and computing; and 5) advanced adaptive multidimensional and array signal processing. Common to all of these projects is a need for access to fast numerical computation and high resolution visualization and display capabilities. The goal of this project is to set up a state of the art facility for processing, visualization and display of multidimensional data. Towards this end, a computer for high performance numerical computation, and a RAM-based workstation for display of high resolution video image sequences with a high performance graphics capability will be purchased. ***

9724567 Sawchuk, Alexander McLeod, Dennis University of Southern California High Performance of Processors and Networks for Video Compression, Distributed Visualization, Database Systems and Collaborative Telepresence USC has received a Major Research Instrumentation award for the acquisition of processing hardware; a special purpose high-speed-resolution digital video storage and display hardware; and miscellaneous data communications hardware; for an Integrated Media Research Network (IMRN) to support research and training programs in high-performance multimedia, graphics, visualization, and database systems. Research projects to be supported include the generation, compression and transmission of real-time video over shared networks; processing of remote high resolution 3-D visualization and computation-intensive graphics; robust distribution and networking of interactive multimedia data within a heterogeneous distributed computing environment; distributed database management techniques for video and audio servers; and utilization of multiprocessor computers for collaborative telepresence over long physical distances. Besides making the enhanced facilities available to students pursuing research in high-performance graphics, visualization and database systems, USC plans to connect the IMRN to the Institution's School of Engineering's Instructional Television network which supports two-way live interactive broadcasts of regular credit courses from engineering, computer science and mathematics. It is envisaged that this connection will allow students to work on research projects anywhere on the main campus, medical school campus and USC's Information Sciences Institute and will allow classroom demonstrations over these locations as well as the local Los Angeles area. Research results on database management for video data and distance learning will contribute directly to these distance learning activities.

Abstract EEC-9872823 Nikias This award will fund the purchase of equipment to enhance, augment and expand research and education activities on the Integrated Media Systems Center's (IMSC's) Media Immersion Environment (MIE). The MIE is the centerpiece of the research program and strategic plan of the IMSC, and provides a physical hardware and software framework for the integration of multimedia engineering and scientific developments from IMSC and elsewhere, with broad multidisciplinary applicability to every aspect of the human sensory experience and interpersonal interactions. Special purpose equipment will be purchased to enable the continued evolution of the MIE concept.

This award provides funding in partial support of acquisition of equipment to upgrade the network infrastructure of the Integrated Media Systems Engineering Research Center (IMSC) at the University of Southern California from the existing local area network to a wide area network. The equipment is being used to establish a new telepresence laboratory, improve the performance and lower the cost of realistic, textured, animated rendering and avatar data extraction for telepresence applications to support multimedia research. The equipment includes ATM Network hardware upgrades and connections to the Next Generation Internet, real-time encoders/decoders for full D1-rate video compression, high performance graphics workstations, network attached storage, wireless ultra-wideband impulse radio transceivers, and 3D immersive display an eye human-computer interface devices. The facilities will enable more than 25 faculty and staff and more than 100 students to attack the hardware and software barriers that limit the creation, dissemination, and access to multimedia information. The equipment will support multidisciplinary research and education in the process of solving cutting-edge systems-level problems that require final solution assessment by design, simulation, and implementation.

EIA-0116573
Alexander A. Sawchuk
University of Southern California

MRI: Acquisition of Equipment for Remote Multichannel Media Immersion

This is a proposal for equipment acquisition under the Major Research Instrumentation (MRI) program to support research and student training in immersive technology. Immersive technology is the creation of the aural and visual ambience of a virtual space in which individuals can experience remote events or communicate naturally with others located remotely.

This research focuses on the development of a sound theoretical framework for the design of efficient network discovery and reconfiguration techniques that are deadlock-free and generically applicable to state-of-the-art interconnection networks used in future multiprocessor servers, network-based
computing clusters and distributed storage systems. The theory should have wide applicability and serve as an authoritative basis on which deadlock freedom of reconfiguration processes for arbitrary networks can be formally proved. As part of the theoretical framework, a general methodology will be developed that will allow the power of the theory to be realized in the straightforward design of new and more efficient techniques. The techniques derived from the theory and methodology will provide alternative ways of increasing network reliability, availability, and serviceability (RAS) in the presence of unconstrained fault patterns as well as in the presence of voluntary changes to a network configuration due to resource re-partitioning, communication-aware algorithm/process re-mapping, data migration, etc.

The techniques will not impede the injection, transmission, or delivery of user packets during discovery and reconfiguration processes but, rather, will remain relatively transparent to the user and/or system administrator. Proof of concepts will be pursued by simulating the developed techniques and applying them to state-of-the-art switch-based system-area and storage-area networks amenable to their implementation. This research ultimately could result in new opportunities for dependable network architectures to off-load some of the QoS handling to lower network layers while, at the same time, providing enriched RAS features and higher performance.

This project, developing the technology for Distributed Immersive Performance (DIP), deals with live, interactive musical performances in which participants in different physical locations are interconnected by very high fidelity multichannel audio and video links. DIP, a specialized realization of broader immersive technology, creates the complete aural and visual ambience that places a group in a virtual space to experience events occurring at a remote site or communicate naturally regardless of location. The assembled DIP experimental system will have three sites in different locations on the USC campus. The sites will have different types of equipment to test the effects of video and audio fidelity on the ease of use and functionality of different applications. Two will have high-definition (HD) video or digital video (DV) quality images projected onto wide screen wall displays completely integrated with an immersive audio reproduction system for a seamless, fully 3-dimensional aural environment with the correct spatial sound localization for participants. The system will be capable of storage and playback of the many streams of synchronized audio and video data (immersidata) and will utilize novel protocols for the low-latency, seamless, synchronized real-time delivery of immersidata over local-area and wide-area networks such as Internet. Partners in the project include New World Symphony (NWS) of Miami Beach, University of Maryland, and Georgia Tech. The latter two contribute the Internet2 infrastructure as server sites. The enabled research addresses the following challenges:
Low latency continuous media (CM) stream transmission, synchronization and data loss management
Low latency, real-time video and multichannel immersive audio acquisition and rendering
Real-time continuous media stream recording, storage, playback
Human factor studies: psychophysical, perceptual, artistic, performance evaluation
Robust integration of all these technical areas into seamless presentation to participants
Students participate in the assembly, integration, testing, and research applications using the DIP system via thesis research, directed research projects, and classroom work. Offering an opportunity for students to receive a broad cross-disciplinary education in media systems engineering, undergraduate engineering majors from USC and CSULA are invited to participate.

Project Abstract:

In this research, we develop efficient congestion control
mechanisms for high-performance interconnection networks used in
multiprocessors, distributed network-based multicomputer clusters,
storage systems, and IP router fabrics. Techniques will be
explored that allow rapid advancement of packets directly involved
in network congestion. Our approach is based on adding minimal
intelligence to routers and network interfaces---in the form of
speculative scheduling capability---such that resources are maximally
utilized while packets are efficiently routed. This can be done by
more effectively steering packets around congested areas and by more
precisely detecting and handling potential deadlock situations arising
from cyclically-correlated congestion on a closed set of resources.
A by-product is that global expansion of congestion trees/cycles which
can seriously degrade performance is prevented. In addition to
developing formal theoretical support for the approach, detailed
evaluations will be carried out through modeling and simulation.

The significance of this research is two-fold. First, by effectively
dispersing packets out of congested regions of the network, higher
sustained throughput and lower, more predictable latency can be
achieved. That is, more data can be sent and received through the
network over a given period of time, and the time it takes for the
network to deliver the data can be reduced, with less variability.
Second, by efficiently resolving deadlock in the network, the
routing of packets is guaranteed never to come to a halt. These
important factors allow computer applications which require a great
amount of communication between system components to run much
faster and dependably.

Abstract
0541417
Alexander Sawchuk
Los Angeles, CA

Investigation of Reliability - Constrained On-Chip Networks

Among the many challenges computer architects will face over the next decade and beyond is the growing demand for reliable on-chip communication between system microarchitecture functional domains. Continued increases in scaling and integration of transistor and wiring resources are allowing more system functions to be implemented on chip, but also more circuit defects and variability. Recent trends toward partitioning the system microarchitecture into multiple on-chip compute domains in the form of functional unit blocks, tiles and processor cores mitigate chipcrossing delays and facilitate chip survivability. That is, it helps to prevent system performance and cost from being encumbered by deep submicron technology scaling. With these developments, support for low latency, high throughput, and fault tolerant communication is becoming more and more critical within the on-chip network used to interconnect the compute domains. Much recent research is directed toward the design of on-chip networks to meet certain cost/performance goals
(chip area, latency and throughput), but very little architecture research explores on-chip network
reliability issues specific to the problem of hard faults, which is recognized as a growing problem.
In this research, we investigate reliability challenges and techniques for on-chip networks that will meet manufacturing yield and chip reliability targets as technology scales into the deep submicron regime. The goal is to understand the problem more fully and to develop on-chip network techniques for efficient resource and reliability management, fault isolation, dynamic reconfiguration and fault recovery to allow fault-stricken microarchitectures partitioned across a chip to have increased usability and prolonged life. We endeavor to increase understanding of chip failure mechanisms (their causes and impact); appropriately model them as related specifically to on-chip networks; develop approaches and techniques that will allow on-chip networks (in cooperation with techniques for other components of the chip microarchitecture) to be resilient to
hard faults; evaluate and assess the benefit of the proposed techniques under expected workloads and common-case operational conditions; and, furthermore, understand the tradeoffs in using the proposed fault-resilient on-chip network techniques that is, identify those situations in which various techniques can be most usefully applied given the existence of other possible constraints. The Intellectual Merit of this research is substantial. The research is timely as it addresses an important issue that will only worsen with continuing advancements in technology scaling. The research will culminate with key contributions made in (1) increasing our understanding of the fundamental design, process, and operational mechanisms most responsible for on-chip interconnect failures and (2) producing original and promising techniques for increasing on-chip interconnect reliability and chip reliability as a whole. Beyond the specific results produced by the models and simulation environments we will develop through this project, these tool artifacts will likely have a profound impact on future research infrastructure and education for years to come. They
will be invaluable assets to researchers, students, and practitioners for understanding, developing,
evaluating, and trading-off alternative reliability techniques as demanded by advanced technologies and systems. The tools we develop will be made publicly available and are expected to have widespread use. The results of this research will also be widely disseminated through publications. The Broader Impact of this research is significant and far-reaching. This research can have a profound impact on the success of near-future nanoscale technologies (molecular, quantum, etc.) used to implement integrated circuits beyond the CMOS era as ICs implemented in these technologies are expected to have substantially more hard faults (orders of magnitude) than CMOS ICs. Reliability techniques such as the ones that will be derived from this research will be critical to systems implemented in these technologies as well as those implemented in future deep submicron technology. In the nearer term, many of the ideas coming from this research may be transferrable to system-level networks, where form-factor constraints often are not as rigid as they are on-chip.