Sarma Vrudhula - US grants

This research is on developing models for evaluating hierarchal testability of circuits. Three topics are being pursued. First, stochastic models for circuit structure, used for obtaining analytical expressions of controllability and observability, are being explored. New testability metrics and fast testability evaluation of IC's based on the stochastic models are being investigated. Second, a unified framework for expressing hierarchal testability metrics is being established. This allows representation of any testability metric for the purpose of hierarchal testability analysis. Formal methods of composing testability metrics are being developed. Third, efficient algorithms for doing the partitioning for testability are being designed and evaluated. Central to the approach is the development of a discrete hazard function that quantifies for each level in a circuit the difficulty to fault propagation exhibited by the circuit structure.

9351291 Vrudhula The aim of this project is to establish an undergraduate digital systems design laboratory with emphasis on VLSI. This laboratory is part of a new two- course sequence offered to seniors in computer engineering. The primary objectives of this project are: (1) to expose the students to all aspects of systems design, starting from the behavioral level down to the layout level; and (2) to teach the fundamental engineering discipline involved in evaluation, testing and redesign. These primary objectives are being achieved by addressing the following important aspects of systems design: (1) use of multiple levels of abstraction; (2) methods of evaluating a design in terms of performance, area, design time and cost at each level; (3) examining tradeoffs among the possible choices that are available at each level; (4) understanding the limits of fabrication technology, causes and effects of failures and fault models; and (5) understanding that design and test cannot be separate activities by introducing design for testability. The purpose of the laboratory is to provide hands on experience through the use of the latest CAD tools and a computing environment that reflects the state-of-the-art in industry. The tools eliminate much of the mundane aspects of the design and allow the students to focus on the important high level design issues. Theoretical knowledge and practical design experience are carefully balanced through a set of realistic design projects that involve the students in all aspects of systems design. In addition, the laboratory provides for rapid prototyping of the designs through the use of Field Programmable Gate Arrays. This allows students to build, exercise, and re-evaluate designs. ***

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This project is carried out as a part of the NSF Research Centers - Small Firms Collaborative R&D initiative, under the leadership of the Center for Low Power Electronics, a S/IUCRC established by the National Science Foundation.

The project is aimed at developing a novel architecture for the rapid prototyping of mixed-signal (analog and digital) systems. The system will be designed using the recently developed dynamic and partially reconfigurable field programmable logic arrays (DPGA) and reconfigurable field programmable analog arrays (FPAA). They not only allow time-multiplexing of different tasks that are mapped on the same silicon area, but also allow overlapping of active computation in one section with configuration of another section of the chip. The granularity at which the reconfiguration can be applied can be a single programmable cell logic block. A development board and associated CAD software tools will be build that will permit the design of mixed-signal systems. A key feature of the system is that part of the computation can be performed in the analog domain and part of it can be performed in the digital domain. The development board will include a microprocessor and associated hardware interfaces to control the two arrays. The project is a collaborative effort of the Center for Low Power Electronics and Western Design Center (WDC), one of its small business partners. The mixed-signal development system (board and software) will be manufactured and commercialized by WDC. The system will also be distributed to university teaching and research laboratories to be used as a vehicle for the rapid prototying of analog, digital and mixed-signal circuits.

As CMOS technology enters the nanometer-regime, one of the most fundamental challenges will result from the loss of predictability of design behavior due to both variations during manufacturing and interferences between components during normal operation. As features on the die continue to shrink, control of the physical parameters, such as the feature size of transistors, their doping levels, and oxide thickness, will become increasingly difficult to control, resulting in dramatic increased uncertainty in the electrical characteristics of individual devices. Also, the close proximity of devices to each other will give rise to significant interference from elements surrounding a device, due to inductive and capacitive coupling, and due to environmental factors, such as power supply and temperature fluctuations. The increase in the number of uncertainties, as well as their severity will result in a general loss of predictability in nanometer-CMOS design and will threaten the ability to produce robust designs.

In this project, we are developing a statistical framework for analysis and optimization of system performance, power, and functional integrity, as well as their newly emerging trade-offs in nanometer design. In the presence of variations due to process fluctuations and environmental interferences, signals are inherently stochastic as are the basic measures of design quality, such as delay and power. The research is therefore investigating the development of stochastic models for performance metrics that capture their dependence on the various sources of uncertainty. The new design methodology will focus on robustness as a new measure of design quality, including delay, power consumption and measures of functional integrity, and will allow these design objectives to be constrained at prescribed levels of confidence. Furthermore, the research team is considering new methods for simultaneous optimization of performance, energy, and functional integrity that effectively exploit new trade-offs and interactions between these objectives in nanometer design.

Moore's law based doubling of transistor counts and decreasing feature sizes have resulted in a phenomenal increase in performance at the expense of an exponential increase in power consumption
and consequently, heat generation. Scaling according to Moore's law cannot continue unless system-level solutions for power and thermal management are developed. Existing techniques for system-level
power optimization including dynamic power management (DPM) and dynamic voltage frequency scaling (DVFS) operate in a piece-meal fashion and are sub-optimal in general. Thermal management schemes, to date, are also fairly simple and do not interact with DPM or DVFS policies that control the power consumption and therefore heat generation.

This research will provide a unified framework for energy and thermal management of multi-component computing platforms. The framework will be built around optimal analytical solutions to generic
problem formulations that will be applicable at multiple levels of computing system abstraction. The abstraction levels will include board level, multi-processor system-on-chip level and micro-architecture
pipeline level. The energy and thermal management strategies developed here will reduce the packaging and cooling costs and increase the lifetime of all computing systems -- from portable devices to high
performance desktops to servers. Furthermore, this research will train students in the diverse fields of energy management of microelectronic systems and thermal management of electronic and non-electronic components.

Full Center Proposal for an I/UCRC for Embedded Systems

0856090 Arizona State University; Sarma Vridhula
0856039 Southern Illinois University at Carbondale; Spyros Tragoudas

Embedded systems are application specific computing systems that have and continue to permeate across every facet of human and machine interaction. Home appliances, mobile hand-held devices, medical instrumentation, etc are just a few examples where embedded computing systems are found today. The proposal is to establish a Center to conduct research on robust, energy efficient and networked embedded systems. The lead of the proposed Center will be Arizona State University (ASU)) with site location at Southern Illinois University at Carbondale (SIUC). The main activities of the proposed Center will encompass fundamental, industry relevant research, education and training for undergraduate and graduate students through research projects and directed industry sponsored internships, and technology transfer made possible by shared IP arrangements and student employment. The formation of the proposed Center will significantly enhance the existing research collaboration and greatly leverage the research capabilities of the participating institution and industrial partners.

The research activities at the proposed Center would have direct contribution to the following broad domains: Health Care, Homeland Defense, Energy and Environment, and Education and Culture. The proposed Center will encourage collaboration, and the research will expose students and faculty to state-of-the-art research projects of value to the industry. Graduate and undergraduate students at the participating universities and engineers from the various industrial members will benefit from the I/UCRC infrastructure and industry-driven research and development projects. Both schools have an excellent track record of getting under-represented populations involved in science, engineering and mathematics.

Project Id: 0702831 and 0702628
PI(s): Sarma Vrudhula and Spyros Tragoudas
Title: Synthesis, Verification and Testing for Nano-CMOS and Beyond using Threshold Logic
Institutions: Arizona State University &

ABSTRACT

By 2020, when thickness of Silicon will be less than a stack of a few atoms, the Semiconductor Industry Association roadmap predicts that further scaling CMOS circuits will not be sustainable, and expects a transition from CMOS to one or more of the presently nascent nano technologies such as resonant tunneling diodes (RTD), carbon nanotube FETs (CNFET) and carbon nanowires. Further in the future are devices such as single electron transistors (SET), and quantum cellular automata (QCA). An important and distinctive characteristic of these post-CMOS nano technologies is that they make it possible to efficiently and naturally implement threshold logic (TL). While TL concepts have been known since the 1960s, there has been no comprehensive work on synthesis and optimization of large TL networks similar to what we have witnessed over the past 30 years for traditional CMOS logic gate networks.

This is a proposal to develop a comprehensive design methodology encompassing synthesis, optimization, verification, and testing of TL networks. We propose to investigate synthesis algorithms that start with a technology independent, functional description of the circuit. Optimization of TL networks poses unique problems. Regardless of the underlying technology, TL gates are realized by comparing the weighted sum of the inputs with a given threshold. This can be a comparison of voltages or currents. Since process variations can change the outcome of such a comparison, they not only effect the performance and power but can also change the function realized by the gate. We refer to this as the functional yield (FY). We will develop new algorithms that jointly maximize the FY, power consumption, and performance of a TL network over the space of process variables, e.g. device lengths, widths, threshold voltages, oxide thicknesses, etc. Methods for testing the manufactured circuit for functional correctness and delay using new parametric fault models will also be developed. Verifying the equivalence of a TL network to a given a functional specification has not yet been addressed. This is essential for verifying the result of the synthesis procedure as well as in determining the functional yield when the design parameters are represented as statistical quantities as models of process variations. Expected outcomes of this effort include: new CMOS and post-CMOS circuit architectures for TL gates; algorithms and tools to automatically synthesize, perform functional verification and generate test patterns for TL circuits; methods to compute the parametric yield of TL networks, modeling TL network parameters as correlated random variables; methods to perform joint optimization of functional yield, power consumption and performance of TL networks over the space of process variables.

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).

Wireless sensor networks (WSNs) are becoming pervasive in both civilian and military domains. Low cost and ease of deployment of these networks necessitate the use of batteries as the primary source of power. As a result, battery capacity has emerged as a critical design parameter for maximizing the operational lifetime of the network. In this project, a comprehensive battery-charge-oriented framework for energy management in WSNs is developed. Its key novelty is its accounting of unique nonlinear battery characteristics, including passive recharge, load-profile dependence, and capacity fading. Such characteristics have significant impact on the usable battery capacity, and consequently on the network lifetime. Novel, physically justified analytical models for battery charge/discharge are exploited in designing adaptive control strategies for data processing and communications in a WSN, with the aim of maximizing the network lifetime. These strategies are used to operate individual nodes as well as a hierarchical network of nodes. Battery-aware adaptivity is performed on CPU voltage/frequency, RF transmission power, transmission rate/modulation scheme, sleep/wakeup scheduling, cluster-head assignment, cover selection, etc. Models and algorithms developed in this project are validated and their feasibility demonstrated through simulations and experimentation. The activity includes an education component involving undergraduate and graduate students, and a strong technology transfer plan. The project is expected to lead to novel designs and control strategies for sensor networks, with significantly longer operational lifetime and highly efficient energy management.

The proposed research targets the investigation of techniques that enable using Threshold Logic (TL) circuits to implement Systems on a Chip (SoC) devices for embedded systems. The project proposes to take a unified approach to simultaneously address TL circuit synthesis and TL gate design. The work also plans to investigate TL based on nanodevices and the extension of TL to mixed signal circuits such as Analog to Digital Converters (ADCs). This work also represents the first collaborative project between these two sites of the center.

The outcomes of the proposed work have the potential to help the semiconductor industry produce more reliable and affordable microprocessors and SoC implementations. The work is supported by the Industry Advisory Board as well as individual industry members of the center and has the potential to extend the centers portfolio through collaboration of two of its sites. The PIs research will impact diverse undergraduate and graduate students as well as be used as a tool to recruit students to the field.

This Partnership for Innovation project from Arizona State University is aimed at developing a new approach to digital system design in order to significantly reduce the power consumption and size of digital systems without reducing their speed of operation. If successful, the results of this research can be used to improve the energy efficiency of nearly every digital system, including desktop computers, laptops, tablets, cell phones and other handheld digital devices. This new approach employs threshold logic gates, which compute logic functions in a manner that is distinctly different from the way conventional logic gates operate. A threshold logic gate implements a complex logic function in a single primitive cell, which would otherwise require a network of many conventional logic gates. It is this absorption of logic into a single cell that is the reason for the reduction in power and size. A novel architecture for a threshold logic gate, called a differential threshold logic latch (DTLL), is proposed as the primitive logic cell.
DTLL cells are compatible with existing logic gates, and can be used to replace parts of a digital circuit to reduce its power and area and possibly improve its speed. The resulting circuit will be a hybrid, consisting of DTLL cells and conventional logic gates. A significant advantage of the proposed approach is that DTLL cells can be implemented as efficiently as standard cells, making it possible to integrate threshold logic technology with existing Application Specific Integrated Circuit (ASIC) design methodology. To enable the integration of threshold logic with conventional ASIC design requires the development of design infrastructure, which includes the design of a threshold cell library, and a host of algorithms and software tools that transform existing digital designs into hybrid designs. This project will build such an infrastructure.

The broader impacts of the project will be benefits to performance of mobile electronic applications such as smart phones, cameras, laptops, etc. These devices will benefit the most from a reduction in power consumption delivered as a result of this project. A fundamental advantage of the approach taken in this project to reducing power consumption is that the technology of threshold logic is compatible with existing logic. As a result, the proposed approach is fully compatible with existing industrial design methodology. No new fabrication technology will be required, and existing commercial back-end design tools (e.g., synthesis, optimization, placement and routing) can be used for the hybrid netlists.

Partners at the inception of the project: the knowledge enhancement partners (KEP): Lead institution: Arizona State University (Ira A. Fulton Schools of Engineering and School of Computing, Informatics and Decision Systems Engineering); and Small Businesses: Cactus Semiconductor Inc. and Everspin Inc. Other Partners--Large Businesses: Qualcomm and Texas Instruments.

The NSF I/UCRC Center for Embedded Systems (CES), was established in 2009 as a collaborative effort of Arizona State University (lead) and Southern Illinois University at Carbondale, to perform the industry relevant research for advancing the field of Embedded Systems (ES) hardware and software. It commenced its fifth year of operation of Phase I in Fall 2013. This proposal is for continuation of the CES as a Phase II I/UCRC. During Phase I, CES organized its research program into six main research topics, (1) Power, Energy and Thermal-Aware Design, (2) Electronic System-level (ESL) Design and Technologies, (3) Embedded Multicore Architectures and Programming, (4) Embedded Software Systems, (5) Cyber-Physical Systems, and (6) Integrated Circuit Technologies, Design, and Test. It has conducted fundamental, industry-relevant research, with 70 industry funded projects from 17 companies, involving average of 12.6 faculty, and 26.4 graduate students per year. Industry sponsored student internships have led 50 permanent, full time positions. In Phase II, CES will build upon the ongoing research efforts and cover new topics within these areas, and possibly re-balance its emphasis based on the existing and new industry partners, and additional faculty. Specifically, new projects are expected involving emerging nanotechnologies such as memristors and spintronic devices; a greater emphasis on energy harvesting techniques for ultra-low power systems; more projects addressing security and trustworthiness; design techniques and tools for guaranteeing provably correct behavior; and new computation paradigms that perform decision making in the presence of uncertainty. The research conducted at CES addresses many of the challenging problems posed by ES, the solutions to which can be applied to other design microelectronic system platforms.

The multi-disciplinary nature of the work, and the diversity of the faculty expertise and the industrial partners will result in societal impact of CESs research outcomes. For instance, CES? work on improving the energy efficiency of ES hardware and software, improves and expands battery powered devices for medical applications and consumer electronics, and can also significantly improve the energy efficiency of high performance servers, thereby reducing the damage to the environment. Similarly, CES? work in verification of hybrid systems is being used to ensure that controls systems in automobiles will operate correctly. The same technologies will be used in all sorts of safety critical systems. CES? work on sensors for monitoring bridges is yet another example of the far reaching societal benefits of its research program. CES maintains a popular internship program at ASU for both undergraduate and graduate students. CES graduate students have learned the necessity and importance of explaining and justifying their work to industry members in a public forum with limited time and to an audience with varied backgrounds. This has made them and their work enormously more marketable to industry. Finally, both ASU and SIUC have successfully inducted outstanding female faculty, and CES will continue this effort in Phase II. In Phase II it is expected that at least one new site (Northeastern University) will be added to CES and continued efforts will be made to expand CES? industrial membership following a strong marketing plan that has been developed to achieve set targets. In addition, CES will explore the possibility of adding one or possibly two international sites: the University of Patras (UoP) in Greece, and the Indian Institute of Science (IISc), Bangalore, India. UoP officials are expected to attend the January 2014 meeting of CES, and IISc has expressed interest in exploring ways to become a I/UCRC site, through their recently established Robert Bosch Center for Cyberphysical Systems.

A significant challenge for embedded systems is developing the high-performance, reliable, low cost, and low-power integrated circuits. This project addresses this challenge by developing accurate testability and timing analysis techniques for integrated circuits. The main objective of this effort is to address timing-related reliability, testing and design challenges faced by the semiconductor industry due to significant increase in process variations. The project will develop new methods for modeling the process variability that benefit from advanced data structures and novel algorithms. A new direction in determining gate delay models in the presence of process variations is investigated. The goal is to reduce modeling errors and is expected to identify critical path delay faults that current methods skip. Moreover, it is expected to result in more accurate estimates for the delay of the circuit.

The proposed research activities will help semiconductor companies in developing reliable and faster integrated circuits and microprocessors. This will have impact on the society since cell-phones, cars, airplanes, unmanned vehicles, and biomedical devices are a major factor in the quality of human life. The fundamental modeling of process variations will be developed with the center member companies, ensuring rapid technology transfer and uptake of new methods. The work is supported by the Industry Advisory Board as well as individual industry members of the center and has the potential to extend the center research portfolio while potentially attracting new members. The proposed research will be used as a vehicle to help students develop interests and abilities to conduct research in the VLSI design and test automation area, and undergraduates will be inspired for graduate studies.

This project will develop foundations for novel design of low-power and high-resolution image sensors, beyond the state-of-the-art. The potential outcome of this research is two orders of magnitude power reduction and ability to achieve real-time image reconstruction. The research activities have the potential to make significant impact on number of different industries. Image sensors have been used in extremely wide range of applications to directly enhance the quality of human life, including communication, entertainment, security, medical diagnosis and many others. The PI's will involve a number of graduate and undergraduate students from under-represented groups.

This project will systematically investigate the optimal designs of all major blocks used in image sensors. The project aims to develop novel design ideas for compressive sensing, resulting in potential order-of-magnitude improvements in trade-offs between energy use and performance. The research will be conducted within the I/UCRC Center for Embedded Systems and the project has Center's strong support, and active participation from its member companies, which will pave the way for the transition of the project outcomes into commercial products that will benefit society at large.

Digital circuits made up of transistors are the components inside computer chips that operate nearly all the computing devices (e.g. servers, desktops, laptops, tablets, smartphones, and wearables) in use today. Although we can pack more than a billion transistors in one square centimeter, it is becoming increasingly difficult to make full use of them because they consume too much energy. Today, methods to lower the energy consumption always come with a price?reduced speed, which in turn makes them less capable to perform more challenging tasks (e.g. face recognition by smartphone). This team has developed a new way to design digital circuits that consume much less energy (ranging from 20% to 40%) without sacrificing performance and can be made smaller. Thus the proposed technology will reduce energy consumption of digital systems, extend the battery life and/or improve the capabilities of laptops, tablets, smartphones and other battery powered systems. Another significant advantage of the proposed circuits is that they can be designed with the same commercial tools and the same semiconductor fabrication processes that are used by companies today,
enabling easy and rapid adoption by industry.

High performance, low-­‐power digital circuits are required for a large class of products including smartphones and wearables. Current semiconductor solutions rely on clock and power management to reduce energy consumption, but reduction in energy per operation has relied on technology scaling with diminishing returns. This I-Corps team has developed a digital circuit implementation technology, that reduces joules/operation and area without compromising speed, and is based on three fundamental advances in CMOS logic design, all patent protected. (1) Robust, low power threshold logic circuit design, (TLG), that combines the functionality of a large set of complex functions, and a flip-­‐flop into a single cell. (2) A standard cell library of TLGs, which is perfectly compatible with conventional cell libraries used by commercial synthesis, optimization and physical design tools. (3) Software that optimizes a given logic network using cells and conventional logic cells, resulting in a hybrid design. All three - the circuit architecture, cell library and design software - were designed to ensure 100% compatibility with existing commercial design flows, allowing fully automated synthesis, optimization and layout using commercial tools.

This PFI: AIR Technology Translation project focuses on translating a recent innovation of designing digital circuits with threshold-logic circuits to fill the need for achieving reductions in power consumption and size of digital systems, at advanced technology nodes. The threshold-logic circuits and the concomitant design methodology is important because, from a user's perspective, it will enable mobile systems such as laptops and smartphones to operate much longer between recharging of the batteries, and reduce their size and weight. It can also lead to reducing the energy usage of bigger systems such as desktop computers, and massive data centers. From a manufacturer's perspective, it can result in cost savings, improved reliability and more competitive products. The project will result in enhanced design tools, the design of threshold-logic primitive cells, and the design of a prototype circuit at least one advanced technology node to serve as a proof-of-concept of its robustness and scalability at lower geometries.

This threshold-logic based digital design technology has the following unique features: (1) a new architecture and method of operation of certain digital circuit primitives, and (2) a new way of incorporating them automatically in larger circuits using existing design tools, i.e., without disrupting the existing design methodologies, so that it can be easily adopted by industry. These features provide the following advantages: smaller circuits, lower dynamic power consumption, lower standby power consumption, and lower variations in power, all without sacrificing speed, when compared to the leading competing digital ASIC (application specific integrated circuit) technology in this market space.

This project addresses the following technology gap(s) as it translates from research discovery (successfully demonstrated at 65nm node) toward commercial application: the scalability of the technology and design methodology to advanced (smaller geometries- 40nm, 28nm) technology nodes, including overcoming physical design challenges, maintaining robustness to increased process variations, and scaling the accompanying software tools to industrial-scale circuits. These challenges will be addressed by first developing the circuit libraries in 40nm, which is still a key technology for many companies competing in the $1T IoT (internet of things) market, and then advancing to 28nm in FD-SOI. The performance and capability of the design software will be enhanced by developing better interfaces to existing commercial design tools, and use of faster software libraries and commercial software platforms.

In addition, personnel involved in this project, Ph.D. level graduate students, will continue to receive significant training that requires developing a broad range of design and analytical skills, in multiple technical areas, as well as learning how to meet exacting industrial design standards. Other activities will include summer internships with companies that have expressed interest in the threshold-logic technology, visiting companies and presenting and marketing the research outcomes to industry.

Arizona State University will collaborate with The University of Arizona, University of Southern California, Southern Illinois University Carbondale and the University of Connecticut to plan for the formation of a new Industry University Cooperative Research Center (IUCRC), called Center for Networked Embedded, Smart and Trusted Things (NESTT). Companies from a wide spectrum of industries will be recruited and will work jointly with faculty to create a portfolio of industry-ranked, multi-disciplinary research projects to develop innovative solutions to fundamental technological and societal challenges posed by Internet of Things (IoT). The outcome will be a proposal to establish NESTT as an IUCRC.

ASU will work with its partners to organize workshops involving industry leaders and academic researchers to draft the research agenda for NESTT, aimed at accelerating IoT technology development and transfer to industry, and make opportunities from the IoT equitable, safe and secure for all. ASU expertise will include edge and Fog computing; safe and secure cyber-physical systems; machine learning, data analytics; trustworthy, networked embedded systems; robotics and industrial IoT; smart cities and transportation systems; sensors and wearable electronics; IoT governance, technology-related law and ethics, and business models. NESTT at ASU will further the participation of underrepresented students in STEM disciplines.

The IoT will become the foundational technology for every major industry. NESTT?s technological innovations and holistic multi-disciplinary design will lower the barriers to the adoption IoT technologies which will accelerate the delivery of significant economic, societal and environmental returns. The enormous wealth of data generated from such IoT systems will also lead to new discoveries and inventions in many scientific disciplines as scientific communities further embrace data-driven research. The planning for NESTT will include working with industry partners to develop innovative ways for recruiting (in industry and academia) underrepresented students in STEM disciplines.

The agenda and documentation of activities for the NESTT IUCRC planning meetings will be made available on ASU's website for the Center for Embedded Systems (https://embedded.asu.edu ). It will be maintained until the establishment of NESTT, and then merged with the NESTT site.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Humans can seamlessly detect and classify objects from a wide range of complex data sources, and draw inferences to make predictions and decisions. New types of algorithms known as deep neural networks (DNN), are being developed to endow computers with very same capabilities. The present approach of transferring all the data to a remote datacenter and have the algorithms executed there is not sustainable because the amount of data being generated is growing exponentially, is too slow, and can compromise privacy and security. The aim of this project is to enable the execution of complex DNN algorithms at or near the place of data acquisition. Referred to as "AI at the edge", nearly all the leading industries are developing varieties of new "edge devices" to be deployed in the field. This project will develop a framework consisting of technology agnostic software tools that will optimally deploy the DNN algorithms on heterogenous networks of edge devices to maximize their performance and energy efficiency. Domains that will benefit from the outcomes of this project, include retail, security, transportation and logistics, factory automation, healthcare etc. The project team will also include graduate and undergraduate students. Strong effort to recruit students from underrepresented groups will be made. The team will also vigorously pursue various avenues for commercialization.

The aim of this project is to enable "AI at the Edge" using DNN algorithms, which can be trained on any kind of data, in any number of dimensions, and then used to extract valuable information for automated prediction, classification, and decision making. Sophisticated DNN models can involve 100s of layers and tens of millions of parameters. Because training is computation and memory intensive, it is performed on servers. However, for performing inference at the edge, industry is building hardware accelerators that implement DNNs in silicon, integrating them with their mobile Systems on Chips (SoC)s to be deployed at the edge, each with their own architectures, memory organization and neuromorphic engines. Furthermore, complex ML applications will be expressed as heterogeneous Networks of Models (NoMs) of DNNs operating on streaming data. The key challenges to be addressed in this project are to determine how to optimally map NoMs, whose structure keeps changing depending the content of the data, onto a network of heterogeneous edge computing devices. The optimization will involve replicating and pipelining DNN models and deciding on which edge computing device to deploy each instance of a model, all at run-time. Furthermore, this determination will be based on the content of the data stream, the available resources, the characteristics of the communication medium, as well as the present allocation of models to devices. The outcomes of this project will include technology agnostic algorithms and software tools for performing this mapping.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.