Nitin Chandrachoodan, Ph.D.
Affiliations: | 2002 | University of Maryland, College Park, College Park, MD |
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"Nitin Chandrachoodan"Parents
Sign in to add mentor| Shuvra S. Bhattacharyya | grad student | 2002 | University of Maryland | |
| (Performance analysis and hierarchical timing for DSP system synthesis.) | ||||
| K. J. Ray Liu | grad student | 2002 | University of Maryland | |
| (Performance analysis and hierarchical timing for DSP system synthesis.) | ||||
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Publications
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| Bathla S, Rao RM, Chandrachoodan N. (2019) A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits Ieee Transactions On Very Large Scale Integration Systems. 27: 376-386 |
| Potluri S, Trinadh AS, Sobhan Babu C, et al. (2015) DFT assisted techniques for peak launch-to-capture power reduction during launch-on-shift at-speed testing Acm Transactions On Design Automation of Electronic Systems. 21 |
| Potluri S, Chandrachoodan N, Kamakoti V. (2012) Interconnect aware test power reduction Journal of Low Power Electronics. 8: 516-525 |
| Jaiswal MK, Chandrachoodan N. (2012) FPGA-based high-performance and scalable block LU decomposition architecture Ieee Transactions On Computers. 61: 60-72 |
| Parashar KN, Chandrachoodan N. (2007) A novel event based simulation algorithm for sequential digital circuit simulation Proceedings - 2007 International Conference On Field Programmable Logic and Applications, Fpl. 792-795 |
| Chandrachoodan N, Bhattacharyya SS, Liu KJR. (2004) The hierarchical timing pair model for multirate DSP applications Ieee Transactions On Signal Processing. 52: 1209-1217 |
| Raghupathy A, Chandrachoodan N, Liu KJR. (2003) Algorithm and VLSI Architecture for High Performance Adaptive Video Scaling Ieee Transactions On Multimedia. 5: 489-502 |
| Chandrachoodan N, Bhattacharyya SS, Liu KJR. (2002) High-level synthesis of DSP applications using adaptive negative cycle detection Eurasip Journal On Applied Signal Processing. 2002: 893-907 |
| Chandrachoodan N, Bhattacharyya SS, Liu KJR. (2001) An efficient timing model for hardware implementation of multirate dataflow graphs Icassp, Ieee International Conference On Acoustics, Speech and Signal Processing - Proceedings. 2: 1153-1156 |