Puneet Gupta
Affiliations: | Electrical Engineering | University of California, Los Angeles, Los Angeles, CA |
Area:
Design-technology co-optimization, physical design, variability and reliability aware computer architecturesWebsite:
https://samueli.ucla.edu/people/puneet-gupta/Google:
"Puneet Gupta"Parents
Sign in to add mentor| Andrew B. Kahng | grad student | 2007 | UCSD (MathTree) | |
| (On compensation of systematic manufacturing variations in physical design.) | ||||
Children
Sign in to add trainee| Lerong Cheng | grad student | 2010 | UCLA |
| Rani Abou Ghaida | grad student | 2012 | UCLA |
| Abde A. Kagalwalla | grad student | 2014 | UCLA |
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Publications
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| Pal S, Petrisko D, Kumar R, et al. (2020) Design Space Exploration for Chiplet-Assembly-Based Processors Ieee Transactions On Very Large Scale Integration Systems. 28: 1062-1073 |
| Chu E, Luo Y, Gupta P. (2020) Design Impacts of Back-End-of-Line Line Edge Roughness Ieee Transactions On Semiconductor Manufacturing. 33: 32-41 |
| Gupta P, Iyer SS. (2019) Goodbye, motherboard. Bare chiplets bonded to silicon will make computers smaller and more powerful: Hello, silicon-interconnect fabric Ieee Spectrum. 56: 28-33 |
| Gupta RK, Mitra S, Gupta P. (2019) Variability Expeditions: A Retrospective Ieee Design & Test of Computers. 36: 65-67 |
| Wang W, Yona Y, Diggavi SN, et al. (2018) Design and Analysis of Stability-Guaranteed PUFs Ieee Transactions On Information Forensics and Security. 13: 978-992 |
| Wang S, Lee H, Grezes C, et al. (2018) Adaptive MRAM Write and Read with MTJ Variation Monitor Ieee Transactions On Emerging Topics in Computing. 1-1 |
| Wang W, Zhao C, Gupta P. (2018) Assessing Layout Density Benefits of Vertical Channel Devices Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 3211-3215 |
| Gottscho M, Alam I, Schoeny C, et al. (2017) Low-Cost Memory Fault Tolerance for IoT Devices Acm Transactions in Embedded Computing Systems. 16: 128 |
| Badr Y, Gupta P. (2017) Technology path-finding for directed self-assembly for via layers Proceedings of Spie. 10148 |
| Badr YA, Gupta P. (2017) Technology path-finding framework for directed-self assembly for via layers Journal of Micro-Nanolithography Mems and Moems. 16: 13505-13505 |