Ashok Jagannathan, Ph.D.
Affiliations: | 2005 | University of California, Los Angeles, Los Angeles, CA |
Area:
Computer system architecture, energy-efficient computing, reconfigurable computing, electronic design automation, fault-tolerant design of VLSI systems, design for nanotechnologies, design and analysis of algorithmsGoogle:
"Ashok Jagannathan"Parents
Sign in to add mentor| Jason Cong | grad student | 2005 | UCLA | |
| (Microarchitecture evaluation and optimization in interconnect-limited technologies.) | ||||
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Publications
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| Cong J, Han G, Jagannathan A, et al. (2007) Accelerating sequential applications on CMPs using core spilling Ieee Transactions On Parallel and Distributed Systems. 18: 1094-1107 |
| Cong J, Jagannathan A, Ma Y, et al. (2006) An automated design flow for 3D microarchitecture evaluation Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 384-389 |
| Jagannathan A, Yang HH, Konigsfeld K, et al. (2005) Microarchitecture evaluation with floorplanning and interconnect pipelining Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: I8-I15 |
| Cong J, Fan Y, Han G, et al. (2005) Instruction set extension with shadow registers for configurable processors Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 99-106 |
| Cong J, Jagannathan A, Reinman G, et al. (2003) Microarchitecture evaluation with physical planning Proceedings - Design Automation Conference. 32-35 |