Ashok Jagannathan, Ph.D.

Affiliations: 
2005 University of California, Los Angeles, Los Angeles, CA 
Area:
Computer system architecture, energy-efficient computing, reconfigurable computing, electronic design automation, fault-tolerant design of VLSI systems, design for nanotechnologies, design and analysis of algorithms
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"Ashok Jagannathan"

Parents

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Jason Cong grad student 2005 UCLA
 (Microarchitecture evaluation and optimization in interconnect-limited technologies.)
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Publications

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Panda PR, Sharma N, Pilania AK, et al. (2014) Array scalarization in high level synthesis Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 622-627
Cong J, Han G, Jagannathan A, et al. (2007) Accelerating sequential applications on CMPs using core spilling Ieee Transactions On Parallel and Distributed Systems. 18: 1094-1107
Cong J, Jagannathan A, Ma Y, et al. (2006) An automated design flow for 3D microarchitecture evaluation Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 384-389
Cong J, Jagannathan A, Reinman G, et al. (2005) Understanding the energy efficiency of SMT and CMP with multiclustering Proceedings of the International Symposium On Low Power Electronics and Design. 48-53
Jagannathan A, Yang HH, Konigsfeld K, et al. (2005) Microarchitecture evaluation with floorplanning and interconnect pipelining Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 1: I8-I15
Cong J, Fan Y, Han G, et al. (2005) Instruction set extension with shadow registers for configurable processors Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 99-106
Cong J, Jagannathan A, Reinman G, et al. (2003) Microarchitecture evaluation with physical planning Proceedings - Design Automation Conference. 32-35
Lin JY, Jagannathan A, Cong J. (2003) Placement-driven technology mapping for LUT-based FPGAs Acm/Sigda International Symposium On Field Programmable Gate Arrays - Fpga. 121-126
Jagannathan A, Hur SW, Lillis J. (2002) A fast algorithm for context-aware buffer insertion Acm Transactions On Design Automation of Electronic Systems. 7: 173-188
Hur SW, Jagannathan A, Lillis J. (2000) Timing-driven maze routing Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 19: 234-241
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