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Edward Steinberg Davidson

Affiliations: 
University of Michigan, Ann Arbor, Ann Arbor, MI 
 University of Illinois, Urbana-Champaign, Urbana-Champaign, IL 
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Parents

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Gernot Albert Metze grad student 1968 UIUC
 (An algorithm for NAND decomposition of combinational switching functions)

Children

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Janak H. Patel grad student 1976 Stanford (Computer Science Tree)
Andrew Richard Pleszkun grad student 1982 UIUC
Gurindar S. Sohi grad student 1985 UIUC (Computer Science Tree)
Joanne E. DeGroat grad student 1991 UIUC
William H. Mangione-Smith grad student 1991 University of Michigan (Computer Science Tree)
Murali M. Annavaram grad student 2001 University of Michigan
Vijayalakshmi Srinivasan grad student 2001 University of Michigan
Steven A. Vlaovic grad student 2002 University of Michigan
Paul B. Racunas grad student 2003 University of Michigan
Robert S. Chappell grad student 2004 University of Michigan
Mikhail Smelyanskiy grad student 2004 University of Michigan
Alexandre Edouard Eichenberger grad student 2001-2006 University of Michigan

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Publications

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Eichenberger AE, Davidson ES, Abraham SG. (2014) Optimum modulo schedules for minimum register requirements Proceedings of the International Conference On Supercomputing. 227-236
Srinivasan V, Davidson ES, Tyson GS. (2004) A Prefetch Taxonomy Ieee Transactions On Computers. 53: 126-140
Smelyanskiy M, Mahlke S, Davidson ES. (2004) Probabilistic predicate-aware modulo scheduling International Symposium On Code Generation and Optimization, Cgo. 151-162
Annavaram M, Patel JM, Davidson ES. (2003) Call graph prefetching for database applications Acm Transactions On Computer Systems. 21: 412-444
Smelyanskiy M, Mahlke SA, Davidson ES, et al. (2003) Predicate-aware scheduling: A technique for reducing resource constraints International Symposium On Code Generation and Optimization, Cgo 2003. 169-178
Vlaovic S, Davidson ES. (2002) Boosting trace cache performance with NonHead Miss Speculation Proceedings of the International Conference On Supercomputing. 179-188
Vlaovic S, Davidson ES. (2002) TAXI: Trace analysis for X86 interpretation Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 508-514
Tyson GS, Smelyanskiy M, Davidson ES. (2001) Evaluating the use of register queues in software pipelined loops Ieee Transactions On Computers. 50: 769-783
Srinivasan V, Davidson ES, Tyson GS, et al. (2001) Branch history guided instruction prefetching Ieee High-Performance Computer Architecture Symposium Proceedings. 291-300
Tam ES, Vlaovic SA, Tyson GS, et al. (2001) Allocation by conflict: A simple, effective multilateral cache management scheme Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 133-140
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