Xiaoheng Chen, Ph.D.
Affiliations: | 2011 | Electrical and Computer Engineering | University of California, Davis, Davis, CA |
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"Xiaoheng Chen"Parents
Sign in to add mentor| Venkatesh Akella | grad student | 2011 | UC Davis | |
| (Decoder Architectures and Implementations for Quasi-Cyclic Low-Density Parity-Check Codes.) | ||||
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Publications
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| Wang C, Chen X, Li Z, et al. (2013) A Simplified Min-Sum Decoding Algorithm for Non-Binary LDPC Codes Ieee Transactions On Communications. 61: 24-32 |
| Chen X, Wang C. (2012) High-Throughput Efficient Non-Binary LDPC Decoder Based on the Simplified Min-Sum Algorithm Ieee Transactions On Circuits and Systems I-Regular Papers. 59: 2784-2794 |
| Chen X, Lin S, Akella V. (2012) Efficient configurable decoder architecture for nonbinary quasi-cyclic LDPC codes Ieee Transactions On Circuits and Systems I: Regular Papers. 59: 188-197 |
| Chen X, Akella V. (2011) Exploiting Data-Level Parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA Acm Transactions On Reconfigurable Technology and Systems. 4 |
| Chen X, Kang J, Lin S, et al. (2011) Hardware implementation of a backtracking-based reconfigurable decoder for lowering the error floor of quasi-cyclic LDPC codes Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 2931-2943 |
| Chen X, Kang J, Lin S, et al. (2011) Memory system optimization for FPGA-based implementation of quasi-cyclic LDPC codes decoders Ieee Transactions On Circuits and Systems I: Regular Papers. 58: 98-111 |
| Chen X, Lin S, Akella V. (2010) QSN-A simple circular-shift network for reconfigurable quasi-cyclic LDPC decoders Ieee Transactions On Circuits and Systems Ii: Express Briefs. 57: 782-786 |