Ajay N. Bhoj, Ph.D.

Affiliations: 
2013 Electrical Engineering Princeton University, Princeton, NJ 
Area:
Biological & Biomedical,Computing & Networking,Energy & Environment,High-Performance Computing,Integrated Electronic Systems,Nanotechnologies,Quantum Information,Security
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"Ajay Bhoj"

Parents

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Niraj Jha grad student 2013 Princeton
 (Device-Circuit Co-design approaches for Multi-gate FET Technologies.)
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Publications

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Chaudhuri S, Bhoj AN, Bhattacharya D, et al. (2016) Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism Proceedings of the Ieee International Conference On Vlsi Design. 2016: 300-305
Bhattacharya D, Bhoj AN, Jha NK. (2015) Design of efficient content addressable memories in high-performance FinFET technology Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 963-967
Joshi RV, Kim K, Kanj R, et al. (2015) Super fast physics-based methodology for accurate memory yield prediction Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 534-543
Bhoj AN, Jha NK. (2014) Parasitics-aware design of symmetric and asymmetric gate-workfunction finFET SRAMs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 548-561
Bhoj AN, Jha NK. (2013) Design of logic gates and flip-flops in high-performance finFET technology Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 1975-1988
Bhoj AN, Joshi RV, Jha NK. (2013) 3-D-TCAD-based parasitic capacitance extraction for emerging multigate devices and circuits Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 2094-2105
Bhoj AN, Joshi RV, Jha NK. (2013) Efficient methodologies for 3-D TCAD modeling of emerging devices and circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 47-58
Bhoj AN, Simsir MO, Jha NK. (2012) Fault models for logic circuits in the multigate era Ieee Transactions On Nanotechnology. 11: 182-193
Bhoj AN, Joshi RV. (2012) Transport-analysis-based 3-D TCAD capacitance extraction for sub-32-nm SRAM structures Ieee Electron Device Letters. 33: 158-160
Bhoj AN, Jha NK. (2011) Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology Proceedings of the 12th International Symposium On Quality Electronic Design, Isqed 2011. 695-702
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