Navin Srivastava, Ph.D.
Affiliations: | 2009 | Electrical & Computer Engineering | University of California, Santa Barbara, Santa Barbara, CA, United States |
Area:
Computer Engineering/ Electronics & PhotonicsGoogle:
"Navin Srivastava"Parents
Sign in to add mentor| Kaustav Banerjee | grad student | 2009 | UC Santa Barbara | |
| (High-frequency impedance extraction of interconnects considering substrate effects and exploration of single-walled carbon nanotubes for future VLSI interconnects.) | ||||
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Publications
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| Xu C, Srivastava N, Suaya R, et al. (2012) Fast high-frequency impedance extraction of horizontal interconnects and inductors in 3-D ICs with multiple substrates Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1698-1710 |
| Li H, Srivastava N, Mao JF, et al. (2011) Carbon nanotube vias: Does ballistic electron-phonon transport imply improved performance and reliability? Ieee Transactions On Electron Devices. 58: 2689-2701 |
| Srivastava N, Xu C, Suaya R, et al. (2010) Corrections to “Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate” [Jul 09 1047-1060 Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 849-849 |
| Li H, Xu C, Srivastava N, et al. (2009) Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects Ieee Transactions On Electron Devices. 56: 1799-1821 |
| Srivastava N, Li H, Kreupl F, et al. (2009) On the applicability of single-walled carbon nanotubes as VLSI interconnects Ieee Transactions On Nanotechnology. 8: 542-559 |
| Srivastava N, Suaya R, Banerjee K. (2009) Analytical expressions for high-frequency VLSI interconnect impedance extraction in the presence of a multilayer conductive substrate Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 28: 1047-1060 |
| Mysore S, Agrawal B, Srivastava N, et al. (2007) 3D Integration for Introspection Ieee Micro. 27: 77-83 |
| Srivastava N, Banerjee K. (2004) Interconnect challenges for nanoscale electronic circuits Jom. 56: 30-31 |