Seid H. Rasouli, Ph.D.
Affiliations: | 2011 | Electrical & Computer Engineering | University of California, Santa Barbara, Santa Barbara, CA, United States |
Area:
Computer Engineering/ Electronics & PhotonicsGoogle:
"Seid Rasouli"Parents
Sign in to add mentor| Kaustav Banerjee | grad student | 2011 | UC Santa Barbara | |
| (Exploring the Emerging Design and Variability Challenges in Multi-Gate CMOS Devices.) | ||||
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Publications
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| Rasouli SH, Endo K, Chen JF, et al. (2011) Grain-orientation induced quantum confinement variation in FinFETs and multi-gate ultra-thin body CMOS devices and implications for digital design Ieee Transactions On Electron Devices. 58: 2282-2292 |
| Rasouli SH, Xu C, Singh N, et al. (2011) A physical model for work-function variation in ultra-short channel metal-gate mosfets Ieee Electron Device Letters. 32: 1507-1509 |
| Rasouli SH, Dadgour HF, Endo K, et al. (2010) Design optimization of FinFET domino logic considering the width quantization property Ieee Transactions On Electron Devices. 57: 2934-2943 |
| Rasouli SH, Banerjee K. (2010) Effect of grain orientation on NBTI variation and recovery in emerging metal-gate devices Ieee Electron Device Letters. 31: 794-796 |
| Rasouli SH, Endo K, Banerjee K. (2010) Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 714-720 |
| Rasouli SH, Koike H, Baneriee K. (2009) High-speed low-power finFET based domino logic Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 829-834 |
| Rasouli SH, Endo K, Banerjee K. (2009) Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 505-512 |
| Amirabadi A, Chehelcheraghi A, Rasouli SH, et al. (2006) Low power and high performance clock delayed domino logic using saturated keeper Proceedings - Ieee International Symposium On Circuits and Systems. 3173-3176 |
| Seyedi AS, Rasouli SH, Amirabadi A, et al. (2006) Design of domino logic circuits by an optimization method Proceedings of the International Conference On Mixed Design of Integrated Circuits and Systems, Mixdes 2006. 260-263 |
| Abbasian A, Rasouli SH, Derakhshandeh J, et al. (2003) Race-free CMOS pass-gate charge recycling logic (FCPCL) for low power applications 2003 Southwest Symposium On Mixed-Signal Design, Ssmsd 2003. 87-89 |