Jing-Jia Liou, Ph.D.
Affiliations: | 2002 | University of California, Santa Barbara, Santa Barbara, CA, United States |
Area:
Computer EngineeringGoogle:
"Jing-Jia Liou"Parents
Sign in to add mentor| Kwang-Ting (Tim) Cheng | grad student | 2002 | UC Santa Barbara | |
| (Modeling, testing and analysis for delay defects and noise effects in deep sub- micron devices.) | ||||
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Publications
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| Li TY, Huang SY, Hsu HJ, et al. (2013) AC-plus scan methodology for small delay testing and characterization Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 329-341 |
| Chen BS, Hsu CY, Liou JJ. (2011) Robust design of biological circuits: evolutionary systems biology approach. Journal of Biomedicine & Biotechnology. 2011: 304236 |
| Yu LE, Shin C, Paik S, et al. (2011) Sampling correlation sources for timing yield analysis of sequential circuits with clock networks Journal of Circuits, Systems and Computers. 20: 1547-1569 |
| Yang CY, Chen YY, Chen SY, et al. (2010) Automatic test wrapper synthesis for a wireless ATE platform Ieee Design and Test of Computers. 27: 31-41 |
| Chen Y, Liou J. (2008) Diagnosis Framework for Locating Failed Segments of Path Delay Faults Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 16: 755-765 |
| Peng Y, Wu C, Liou J, et al. (2007) BIST-based diagnosis scheme for field programmable gate array interconnect delay faults Iet Computers & Digital Techniques. 1: 716 |
| Wang L, Liou J, Cheng K. (2004) Critical Path Selection for Delay Fault Testing Based Upon a Statistical Timing Model Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 23: 1550-1565 |
| Liou J, Krstic A, Jiang Y, et al. (2003) Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 22: 756-769 |