Balaji Vaidyanathan, Ph.D.

Affiliations: 
2010 Pennsylvania State University, State College, PA, United States 
Area:
Computer Engineering
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"Balaji Vaidyanathan"

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Yuan Xie grad student 2010 Penn State
 (Reliability analysis and optimization for nanoscale System-on-Chip design.)
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Publications

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McMahon W, Mamy-Randriamihaja Y, Vaidyanathan B, et al. (2015) From atoms to circuits: Theoretical and empirical modeling of hot carrier degradation Hot Carrier Degradation in Semiconductor Devices. 3-26
Vaidyanathan B, Oates AS. (2012) Technology scaling effect on the relative impact of NBTI and process variation on the reliability of digital circuits Ieee Transactions On Device and Materials Reliability. 12: 428-436
Vaidyanathan B, Bai S, Oates AS. (2011) The relationship between transistor-based and circuit-based reliability assessment for digital circuits Ieee International Reliability Physics Symposium Proceedings. CR.4.1-CR.4.4
Vaidyanathan B, Wang Y, Xie Y. (2009) Cost-aware lifetime yield analysis of heterogeneous 3D on-chip cache Proceedings of the 2009 Ieee International Workshop On Memory Technology, Design, and Testing, Mtdt 2009. 65-70
Vaidyanathan B, Oates AS, Xie Y, et al. (2009) NBTI-Aware statistical circuit delay assessment Proceedings of the 10th International Symposium On Quality Electronic Design, Isqed 2009. 13-18
Fang YP, Vaidyanathan B, Oates AS. (2009) Soft error rate cross-technology prediction on embedded DRAM Ieee International Reliability Physics Symposium Proceedings. 925-928
Vaidyanathan B, Oates AS, Xie Y. (2009) Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 164-171
Xue L, Kandemir M, Chen G, et al. (2007) Locality-aware distributed loop scheduling for chip multiprocessors Proceedings of the Ieee International Conference On Vlsi Design. 251-256
Vaidyanathan B, Hung WL, Wang F, et al. (2007) Architecting microprocessor components in 3D design space Proceedings of the Ieee International Conference On Vlsi Design. 103-108
Li F, Chen G, Kandemir M, et al. (2007) A process scheduler-based approach to NoC power management Proceedings of the Ieee International Conference On Vlsi Design. 77-82
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