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Bo Yao, Ph.D.

Affiliations: 
2005 University of California, San Diego, La Jolla, CA 
Area:
Computer Science, Electronics and Electrical Engineering
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"Bo Yao"
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Chung-Kuan Cheng grad student 2005 UCSD
 (Physical planning of VLSI layout.)

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Publications

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Zhang L, Zhang Y, Chen H, et al. (2011) On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals Ieee Transactions On Very Large Scale Integration Systems. 19: 520-524
Zhou S, Yao B, Chen H, et al. (2007) Efficient timing analysis with known false paths using biclique covering Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 959-969
Yao B, Chen H, Cheng C, et al. (2003) Floorplan representations: Complexity and connections Acm Transactions On Design Automation of Electronic Systems. 8: 55-80
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