Premkishore Shivakumar, Ph.D.
Affiliations: | 2007 | Computer Sciences | University of Texas at Austin, Austin, Texas, U.S.A. |
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"Premkishore Shivakumar"Parents
Sign in to add mentor| Stephen W. Keckler | grad student | 2007 | UT Austin | |
| (Techniques to improve the hard and soft error reliability of distributed architectures.) | ||||
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| Gratz P, Kim C, Sankaralingam K, et al. (2007) On-chip interconnection networks of the TRIPS chip Ieee Micro. 27: 41-50 |
| Sankaralingam K, Nagarajan R, McDonald R, et al. (2006) Distributed microarchitectural protocols in the TRIPS prototype processor Proceedings of the Annual International Symposium On Microarchitecture, Micro. 480-491 |
| Shivakumar P, Keckler SW, Moore CR, et al. (2003) Exploiting microarchitectural redundancy for defect tolerance Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 481-488 |
| Shivakumar P, Keckler SW, Moore CR, et al. (2003) Exploiting microarchitectural redundancy for defect tolerance Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 481-488 |
| Keckler SW, Burger D, Moore CR, et al. (2003) A wire-delay scalable microprocessor architecture for high performance systems Digest of Technical Papers - Ieee International Solid-State Circuits Conference |
| Shivakumar P, Kistler M, Keckler SW, et al. (2002) Modeling the effect of technology trends on the soft error rate of combinational logic Proceedings of the 2002 International Conference On Dependable Systems and Networks. 389-398 |
| Hrishikesh MS, Jouppi NP, Farkas KI, et al. (2002) The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays Conference Proceedings - Annual International Symposium On Computer Architecture, Isca. 14-24 |