Malgorzata Marek-Sadowska

Affiliations: 
Electrical & Computer Engineering University of California, Santa Barbara, Santa Barbara, CA, United States 
Area:
Electronics and Electrical Engineering
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"Malgorzata Marek-Sadowska"
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Publications

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Yang P, Marek-Sadowska M. (2018) High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators Ieee Transactions On Very Large Scale Integration Systems. 26: 1209-1222
Guan Z, Marek-Sadowska M. (2016) AFD-based method for signal line em reliability evaluation Proceedings - International Symposium On Quality Electronic Design, Isqed. 2016: 443-449
Guan Z, Marek-Sadowska M. (2015) Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence Ieee Transactions On Very Large Scale Integration (Vlsi) Systems
Li DA, Marek-Sadowska M, Nassif SR. (2015) T-VEMA: A Temperature-and Variation-Aware Electromigration Power Grid Analysis Tool Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 2327-2331
Qiu X, Marek-Sadowska M, Maly WP. (2015) Three-dimensional chips can be cool: Thermal study of VeSFET-based 3-D chips Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 869-878
Li DA, Marek-Sadowska M, Nassif SR. (2015) A method for improving power grid resilience to electromigration-caused via failures Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 118-130
Yang PL, Marek-Sadowska M, Maly W. (2015) Performance assessment of VeSFET-based SRAM Proceedings of the 2015 Ieee International Conference On Electron Devices and Solid-State Circuits, Edssc 2015. 79-82
Guan Z, Marek-Sadowska M. (2015) Atomic flux divergence-based AC electromigration model for signal line reliability assessment Proceedings - Electronic Components and Technology Conference. 2015: 2155-2161
Li DA, Marek-Sadowska M, Nassif SR. (2015) Layout aware electromigration analysis of power/ground networks Circuit Design For Reliability. 145-173
Nandakumar VS, Marek-Sadowska M. (2014) System-level floorplan-aware analysis of integrated CPU-GPUs Proceedings - Design Automation Conference
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