Malgorzata Marek-Sadowska

Affiliations: 
Electrical & Computer Engineering University of California, Santa Barbara, Santa Barbara, CA, United States 
Area:
Electronics and Electrical Engineering
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"Malgorzata Marek-Sadowska"
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Publications

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Guan Z, Marek-Sadowska M. (2016) AFD-based method for signal line em reliability evaluation Proceedings - International Symposium On Quality Electronic Design, Isqed. 2016: 443-449
Guan Z, Marek-Sadowska M. (2015) Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence Ieee Transactions On Very Large Scale Integration (Vlsi) Systems
Qiu X, Marek-Sadowska M, Maly WP. (2015) Three-dimensional chips can be cool: Thermal study of VeSFET-based 3-D chips Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 869-878
Yang PL, Marek-Sadowska M, Maly W. (2015) Performance assessment of VeSFET-based SRAM Proceedings of the 2015 Ieee International Conference On Electron Devices and Solid-State Circuits, Edssc 2015. 79-82
Guan Z, Marek-Sadowska M. (2015) Atomic flux divergence-based AC electromigration model for signal line reliability assessment Proceedings - Electronic Components and Technology Conference. 2015: 2155-2161
Nandakumar VS, Marek-Sadowska M. (2014) System-level floorplan-aware analysis of integrated CPU-GPUs Proceedings - Design Automation Conference
Qiu X, Marek-Sadowska M, Maly WP. (2014) Characterizing VeSFET-based ICs with CMOS-Oriented EDA infrastructure Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 495-506
Nandakumar VS, Marek-Sadowska M. (2014) On Optimal Kernel Size for Integrated CPU-GPUS - A Case Study Ieee Computer Architecture Letters. 13: 81-84
Guan Z, Marek-Sadowska M, Nassif S, et al. (2014) Atomic flux divergence based current conversion scheme for signal line electromigration reliability assessment 2014 Ieee International Interconnect Technology Conference / Advanced Metallization Conference, Iitc/Amc 2014. 245-248
Qiu X, Marek-Sadowska M, Maly W. (2013) Designing VeSFET-based ICs with CMOS-oriented EDA infrastructure Proceedings of the International Symposium On Physical Design. 130-136
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