Yajun Ran, Ph.D.
Affiliations: | 2005 | University of California, Santa Barbara, Santa Barbara, CA, United States |
Area:
Electronics and Electrical Engineering, Computer ScienceGoogle:
"Yajun Ran"Parents
Sign in to add mentor| Malgorzata Marek-Sadowska | grad student | 2005 | UC Santa Barbara | |
| (A via -configurable regular fabric for nanometer technology.) | ||||
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Publications
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| Ran Y, Marek-Sadowska M. (2006) Via-configurable routing architectures and fast design mappability estimation for regular fabrics Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 998-1009 |
| Ran Y, Marek-Sadowska M. (2006) Designing via-configurable logic blocks for regular fabric Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 14: 1-14 |
| Ran Y, Kondratyev A, Tseng KH, et al. (2005) Eliminating false positives in crosstalk noise analysis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 1406-1419 |
| Wang K, Ran Y, Jiang H, et al. (2005) General skew constrained clock network sizing based on sequential linear programming Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 24: 773-781 |
| Ran Y, Marek-Sadowska M. (2004) An integrated design flow for a via-configurable gate array Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 582-589 |
| Ran Y, Marek-Sadowska M. (2004) On designing via-configurable cell blocks for regular fabrics Proceedings - Design Automation Conference. 198-203 |
| Ran Y, Marek-Sadowska M. (2004) Designing a via-configurable regular fabric Proceedings of the Custom Integrated Circuits Conference. 423-426 |
| Ran Y, Marek-Sadowska M. (2004) The magic of a via-configurable regular fabric Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 338-343 |
| Ran Y, Marek-Sadowska M. (2003) Crosstalk noise in FPGAs Proceedings - Design Automation Conference. 944-949 |