Riaz Naseer, Ph.D.
Affiliations: | 2008 | Electrical Engineering | University of Southern California, Los Angeles, CA, United States |
Area:
Electronics and Electrical EngineeringGoogle:
"Riaz Naseer"Parents
Sign in to add mentorJeffrey T. Draper | grad student | 2008 | USC | |
(A framework for soft error tolerant SRAM design.) |
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Publications
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Naseer R, Draper J. (2008) DEC ECC design to improve memory reliability in sub-100nm technologies Proceedings of the 15th Ieee International Conference On Electronics, Circuits and Systems, Icecs 2008. 586-589 |
Naseer R, Draper J. (2008) Parallel double error correcting code design to mitigate multi-bit upsets in SRAMs Esscirc 2008 - Proceedings of the 34th European Solid-State Circuits Conference. 222-225 |
Bajura MA, Boulghassoul Y, Naseer R, et al. (2007) Models and algorithmic limits for an ECC-based approach to hardening sub-100-nm SRAMs Ieee Transactions On Nuclear Science. 54: 935-945 |
Naseer R, Boulghassoul Y, Draper J, et al. (2007) Critical charge characterization for soft error rate modeling in 90nm SRAM Proceedings - Ieee International Symposium On Circuits and Systems. 1879-1882 |
Naseer R, Bhatti RZ, Draper J. (2006) Analysis of soft error mitigation techniques for register files in IBM Cu-08 90nm technology Midwest Symposium On Circuits and Systems. 1: 515-519 |
Naseer R, Draper J. (2006) DF-DICE: A scalable solution for soft error tolerant circuit design Proceedings - Ieee International Symposium On Circuits and Systems. 3890-3893 |
Naseer R, Draper J. (2005) The DF-dice storage element for immunity to soft errors Midwest Symposium On Circuits and Systems. 2005: 303-306 |