Shrirang K. Karandikar, Ph.D.
Affiliations: | 2004 | University of Minnesota, Twin Cities, Minneapolis, MN |
Area:
Electronics and Electrical EngineeringGoogle:
"Shrirang Karandikar"Parents
Sign in to add mentor| Sachin Sapatnekar | grad student | 2004 | UMN | |
| (Synthesis and performance prediction of VLSI designs.) | ||||
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Publications
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| Karandikar SK, Sapatnekar SS. (2008) Technology mapping using logical effort for solving the load-distribution problem Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 45-58 |
| Hu S, Alpert CJ, Hu J, et al. (2007) Fast algorithms for slew-constrained minimum cost buffering Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 26: 2009-2022 |
| Karandikar SK, Sapatnekar SS. (2005) Fast comparisons of circuit implementations Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 13: 1329-1339 |
| Karandikar SK, Sapatnekar SS. (2005) Fast estimation of area-delay trade-offs in circuit sizing Proceedings - Ieee International Symposium On Circuits and Systems. 3575-3578 |
| Karandikar SK, Sapatnekar SS. (2004) Logical effort based technology mapping Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 419-422 |
| Karandikar SK, Sapatnekar SS. (2001) Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect Proceedings - Design Automation Conference. 377-382 |
| Karandikar SK, Sapatnekar SS. (2001) Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect Proceedings - Design Automation Conference. 377-382 |