Jun H. Bahn, Ph.D.
Affiliations: | 2008 | University of California, Irvine, Irvine, CA |
Area:
Electronics and Electrical Engineering, Computer ScienceGoogle:
"Jun Bahn"Parents
Sign in to add mentor| Nader Bagherzadeh | grad student | 2008 | UC Irvine | |
| (Design and analysis of Network-on-Chip (NoC) architecture.) | ||||
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Publications
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| Hu WH, Chen CY, Bahn JH, et al. (2012) Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform Iet Computers and Digital Techniques. 6: 86-94 |
| Yang YS, Bahn JH, Lee SE, et al. (2010) Parallel processing for block ciphers on a fault tolerant networked processor array International Journal of High Performance Systems Architecture. 2: 156-167 |
| Bahn JH, Yang JS, Hu WH, et al. (2009) Parallel fft algorithms on network-on-chips Journal of Circuits, Systems and Computers. 18: 255-269 |
| Hu WH, Bahn JH, Bagherzadeh N. (2009) Parallel LDPC decoding on a network-on-chip based multiprocessor platform Proceedings - Symposium On Computer Architecture and High Performance Computing. 35-40 |
| Yang YS, Bahn JH, Lee SE, et al. (2009) Parallel and pipeline processing for block cipher algorithms on a network-on-chip Itng 2009 - 6th International Conference On Information Technology: New Generations. 849-854 |
| Bahn JH, Bagherzadeh N. (2009) On-chip interconnection network with an efficient parallel buffer structure and generic traffic model Scientia Iranica. 16: 104-118 |
| Bahn JH, Lee SE, Yang YS, et al. (2008) On design and application mapping of a Network-on-Chip (NoC) architecture Parallel Processing Letters. 18: 239-255 |
| Bahn JH, Bagherzadeh N. (2008) Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router Iet Computers and Digital Techniques. 2: 63-73 |
| Bahn JH, Bagherzadeh N. (2008) Efficient parallel buffer structure and its management scheme for a robust network-on-chip (NoC) architecture Communications in Computer and Information Science. 6: 98-105 |
| Lee SE, Bahn JH, Yang YS, et al. (2008) A generic network interface architecture for a Networked Processor Array (NePA) Lecture Notes in Computer Science (Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). 4934: 247-260 |