Vasileios F. Pavlidis, Ph.D.

2008 Electrical and Computer Engineering University of Rochester, Rochester, NY 
 2008-2012 Electrical Engineering Swiss Federal Institute of Technology (EPFL) 
 2012- Computer Science University of Manchester, Manchester, England, United Kingdom 
Electronics and Electrical Engineering
"Vasileios Pavlidis"


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Eby G. Friedman grad student 2008 Rochester
 (Interconnect-based design methodologies for three-dimensional integrated circuits.)
Giovanni De Micheli post-doc 2008-2012 Swiss Federal Institute of Technology (EPFL) (Computer Science Tree)
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Papistas IA, Pavlidis VF. (2016) Inter-tier crosstalk noise on power delivery networks for 3-D ICs with inductively-coupled interconnects Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 18: 257-262
Papistas IA, Pavlidis VF. (2015) Bandwidth-to-area comparison of through silicon vias and inductive links for 3-D ICs 2015 European Conference On Circuit Theory and Design, Ecctd 2015
Kalargaris H, Pavlidis VF. (2014) Interconnect design tradeoffs for silicon and glass interposers 2014 Ieee 12th International New Circuits and Systems Conference, Newcas 2014. 77-80
Rahimian S, Pavlidis VF, Tang X, et al. (2013) An enhanced design methodology for resonant clock trees Journal of Low Power Electronics. 9: 198-206
Xu H, Pavlidis VF, Tang X, et al. (2013) Timing uncertainty in 3-D clock trees due to process variations and power supply noise Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 21: 2226-2239
Bobba S, Gaillardon PE, Seiculescu C, et al. (2013) 3.5-D integration: A case study Proceedings - Ieee International Symposium On Circuits and Systems. 2087-2090
Rahimian S, Pavlidis VF, De Micheli G. (2012) Inter-plane communication methods for 3-D ICs Journal of Low Power Electronics. 8: 170-181
Xu H, Pavlidis VF, Micheli GD. (2012) Effect of process variations in 3D global clock distribution networks Acm Journal On Emerging Technologies in Computing Systems. 8
Siozios K, Pavlidis VF, Soudris D. (2012) A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric Acm Transactions On Reconfigurable Technology and Systems. 5
Xu H, Pavlidis VF, Burleson W, et al. (2012) The combined effect of process variations and power supply noise on clock skew and jitter Proceedings - International Symposium On Quality Electronic Design, Isqed. 320-327
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