Aritra Dey, Ph.D.
Affiliations: | 2011 | Electrical Engineering | Arizona State University, Tempe, AZ, United States |
Area:
Electronics and Electrical EngineeringGoogle:
"Aritra Dey"Parents
Sign in to add mentor| David R. Allee | grad student | 2011 | Arizona State | |
| (Mixed Signal design in Thin Film Transistors.) | ||||
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Publications
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| Svensson J, Dey AW, Jacobsson D, et al. (2015) III-V Nanowire CMOS Monolithically Integrated on Si. Nano Letters |
| Dey A, Allee DR. (2012) Amorphous silicon 5 bit flash analog to digital converter Proceedings of the Custom Integrated Circuits Conference |
| Dey A, Avendanno A, Venugopal S, et al. (2011) CMOS TFT Op-Amps: Performance and Limitations Ieee Electron Device Letters |
| Kaftanoglu K, Venugopal SM, Marrs M, et al. (2011) Stability of IZO and a-Si:H TFTs processed at low temperature (200 °c) Ieee/Osa Journal of Display Technology. 7: 339-343 |
| Dey A, Allee DR. (2011) Amorphous silicon current steering digital to analog converter Proceedings of the Custom Integrated Circuits Conference |
| Dey A, Allee DR, Clark LT. (2011) Impact of drain bias stress on forward/reverse mode operation of amorphous ZIO TFTs Solid-State Electronics. 62: 19-24 |
| Dey A, Indluru A, Venugopal SM, et al. (2010) Effect of mechanical and electromechanical stress on a-ZIO TFTs Ieee Electron Device Letters. 31: 1416-1418 |
| Dessai G, Dey A, Gildenblat G, et al. (2009) Symmetric linearization method for double-gate and surrounding-gate MOSFET models Solid-State Electronics. 53: 548-556 |
| Dey A, Chakravorty A, DasGupta N, et al. (2008) Analytical model of subthreshold current and slope for asymmetric 4-T and 3-T double-gate MOSFETs Ieee Transactions On Electron Devices. 55: 3442-3449 |