Ramin Farjad-rad, Ph.D.
Affiliations: | 2000 | Stanford University, Palo Alto, CA |
Area:
Electronics and Electrical EngineeringGoogle:
"Ramin Farjad-rad"Parents
Sign in to add mentor| Thomas H. Lee | grad student | 2000 | Stanford | |
| (A CMOS 4-PAM multi -Gbps serial link transceiver.) | ||||
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Publications
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| Leibowitz BS, Kizer J, Lee H, et al. (2007) A 7.5Gb/s 10-Tap DFE receiver with first tap partial response, spectrally gated adaptation, and 2nd-order data-filtered CDR Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 228-229+599+221 |
| Farjad-Rad R, Nguyen A, Tran JM, et al. (2004) A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os Ieee Journal of Solid-State Circuits. 39: 1553-1561 |
| Ng HT, Lee MJE, Farjad-Rad R, et al. (2003) A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os Proceedings of the Custom Integrated Circuits Conference. 77-80 |
| Ng HT, Farjad-Rad R, Lee MJE, et al. (2003) A Second-Order Semidigital Clock Recovery Circuit Based on Injection Locking Ieee Journal of Solid-State Circuits. 38: 2101-2110 |
| Lee MJE, Dally WJ, Greer T, et al. (2003) Jitter transfer characteristics of delay-locked loops - Theories and design techniques Ieee Journal of Solid-State Circuits. 38: 614-621 |
| Lee MJE, Dally WJ, Poulton J, et al. (2003) A second-order semi-digital clock recovery circuit based on injection locking Digest of Technical Papers - Ieee International Solid-State Circuits Conference |
| Lee MJE, Dally WJ, Farjad-Rad R, et al. (2003) CMOS high-speed I/Os - Present and future Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 454-461 |
| Farjad-Rad R, Ng HT, Lee MJE, et al. (2003) 0.622-8.0Gbps 150mW Serial IO Macrocell with Fully Flexible Preemphasis and Equalization Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 63-66 |
| Farjad-Rad R, Dally W, Ng HT, et al. (2002) A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips Ieee Journal of Solid-State Circuits. 37: 1804-1812 |
| Farjad-Rad R, Dally W, Ng HT, et al. (2002) A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data-communication chips Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 56-57+399 |