Ibrahim Hur, Ph.D.
Affiliations: | 2006 | Electrical and Computer Engineering | University of Texas at Austin, Austin, Texas, U.S.A. |
Area:
Computer Science, Electronics and Electrical EngineeringGoogle:
"Ibrahim Hur"Parents
Sign in to add mentorCalvin Lin | grad student | 2006 | UT Austin | |
(Enhancing memory controllers to improve DRAM power and performance.) |
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Publications
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Eyerman S, Heirman W, Bois KD, et al. (2018) Multi-Stage CPI Stacks Ieee Computer Architecture Letters. 17: 55-58 |
Carlson TE, Heirman W, Eyerman S, et al. (2014) An evaluation of high-level mechanistic core models Acm Transactions On Architecture and Code Optimization. 11 |
Zyulkyarov F, Stipic S, Harris T, et al. (2012) Profiling and optimizing transactional memory applications International Journal of Parallel Programming. 40: 25-56 |
Kestor G, Karakostas V, Unsal OS, et al. (2011) RMS-TM: A comprehensive benchmark suite for Transactional Memory systems Icpe'11 - Proceedings of the 2nd Joint Wosp/Sipew International Conference On Performance Engineering. 335-346 |
Armejach A, Seyedi A, Titos-Gil R, et al. (2011) Using a reconfigurable L1 data cache for efficient version management in hardware Transactional Memory Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 361-371 |
Kestor G, Gioiosa R, Harris T, et al. (2011) STM2: A parallel STM for high performance simultaneous multithreading systems Parallel Architectures and Compilation Techniques - Conference Proceedings, Pact. 221-231 |
Sonmez N, Arcas O, Pflucker O, et al. (2011) TMbox: A flexible and reconfigurable 16-core hybrid transactional memory system Proceedings - Ieee International Symposium On Field-Programmable Custom Computing Machines, Fccm 2011. 146-153 |
Afek Y, Drepper U, Felber P, et al. (2010) The velox transactional memory stack Ieee Micro. 30: 76-87 |
Hur I, Lin C. (2009) Feedback mechanisms for improving probabilistic memory prefetching Proceedings - International Symposium On High-Performance Computer Architecture. 443-454 |
Hur I, Lin C. (2008) A comprehensive approach to DRAM power management Proceedings - International Symposium On High-Performance Computer Architecture. 315-316 |