Can Sitik
Affiliations: | Intel Corporation, Santa Clara, CA, United States | ||
| 2015 | Electrical and Computer Engineering | Drexel University, Philadelphia, PA, United States |
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"Can Sitik"Parents
Sign in to add mentor| Baris Taskin | grad student | 2015 | Drexel | |
| (Dissertation: Design and Automation of Voltage-Scaled Clock Networks) | ||||
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Publications
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| Liu W, Sitik C, Salman E, et al. (2019) SLECTS: Slew-Driven Clock Tree Synthesis Ieee Transactions On Very Large Scale Integration Systems. 27: 864-874 |
| Sitik C, Liu W, Taskin B, et al. (2016) Design Methodology for Voltage-Scaled Clock Distribution Networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems |
| Liu W, Salman E, Sitik C, et al. (2016) Exploiting useful skew in gated low voltage clock trees Proceedings - Ieee International Symposium On Circuits and Systems. 2016: 2595-2598 |
| Rathore M, Liu W, Salman E, et al. (2015) A novel static D-flip-flop topology for low swing clocking Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 20: 301-306 |
| Liu W, Salman E, Sitik C, et al. (2015) Clock skew scheduling in the presence of heavily gated clock networks Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 20: 283-288 |
| Sitik C, Salman E, Filippini L, et al. (2015) FinFET-based low-swing clocking Acm Journal On Emerging Technologies in Computing Systems. 12 |
| Liu W, Salman E, Sitik C, et al. (2015) Enhanced level shifter for multi-voltage operation Proceedings - Ieee International Symposium On Circuits and Systems. 2015: 1442-1445 |
| Sitik C, Filippini L, Salman E, et al. (2014) High performance low swing clock tree synthesis with custom D flip-flop design Proceedings of Ieee Computer Society Annual Symposium On Vlsi, Isvlsi. 498-503 |
| Sitik C, Lerner S, Taskin B. (2014) Timing characterization of clock buffers for clock tree synthesis 2014 32nd Ieee International Conference On Computer Design, Iccd 2014. 230-236 |
| Sitik C, Taskin B. (2014) Iterative skew minimization for low swing clocks Integration, the Vlsi Journal. 47: 356-364 |