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Ping Gui

Affiliations: 
Electrical Engineering Southern Methodist University, Dallas, TX, United States 
Area:
Electronics and Electrical Engineering
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"Ping Gui"
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Parents

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Children

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Peiqing Zhu grad student 2008 SMU
Wickham Chen grad student 2009 SMU
Chen-Wei Huang grad student 2011 SMU
Zheng Gao grad student 2012 SMU

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Publications

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Wang X, Liu T, Guo S, et al. (2020) A 2.56-Gb/s Serial Wireline Transceiver That Supports an Auxiliary Channel in 65-nm CMOS Ieee Transactions On Very Large Scale Integration Systems. 28: 12-22
Wang G, Sun K, Zhang Q, et al. (2019) A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC With Background-Calibrated Fine and Coarse Comparators in 28-nm CMOS Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 27: 1998-2007
Miryala S, Braga D, Christian DC, et al. (2019) CDP1—A Data Concentrator Prototype for the Deep Underground Neutrino Experiment Ieee Transactions On Nuclear Science. 66: 2338-2345
Pan D, Duan Z, Chakraborty S, et al. (2019) A 60–90-GHz CMOS Double-Neutralized LNA Technology With 6.3-dB NF and −10dBm P−1dB Ieee Microwave and Wireless Components Letters. 29: 489-491
Sun K, Wang G, Zhang Q, et al. (2019) A 56-GS/s 8-bit Time-Interleaved ADC With ENOB and BW Enhancement Techniques in 28-nm CMOS Ieee Journal of Solid-State Circuits. 54: 821-833
Yang C, Gui P. (2019) 85–110-GHz CMOS Magnetic-Free Nonreciprocal Components for Full-Duplex Transceivers Ieee Journal of Solid-State Circuits. 54: 368-379
Pan D, Daun Z, Sun L, et al. (2019) Compact and high-linearity 77 GHz CMOS receiver front-end for automotive radar Iet Circuits Devices & Systems. 13: 1203-1208
Guo S, Gui P, Liu T, et al. (2018) A Low-Voltage Low-Phase-Noise 25-GHz Two-Tank Transformer-Feedback VCO Ieee Transactions On Circuits and Systems I: Regular Papers. 65: 3162-3173
Zeng Z, Sun K, Wang G, et al. (2017) A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology Ieee Transactions On Nuclear Science. 64: 1599-1604
Xi T, Huang S, Guo S, et al. (2017) High-Efficiency E-Band Power Amplifiers and Transmitter Using Gate Capacitance Linearization in a 65-nm CMOS Process Ieee Transactions On Circuits and Systems Ii: Express Briefs. 64: 234-238
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