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Bevan M. Baas

Affiliations: 
2003- Electrical and Computer Engineering University of California, Davis, Davis, CA 
Area:
Electronics and Electrical Engineering, Computer Engineering
Website:
https://faculty.engineering.ucdavis.edu/baas/
Google:
"Bevan Marcel Baas" OR "Bevan M Baas"
Bio:

https://www.proquest.com/openview/9faabbf63faac1569bf39d00086d81c6/1

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Parents

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G. Leonard Tyler grad student 1990-1999 Stanford
 (An approach to low-power, high-performance, Fast Fourier Transform processor design)

Children

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Zhiyi Yu grad student 2007 UC Davis
Tinoosh Mohsenin grad student 2010 UC Davis
Zhibin Xiao grad student 2012 UC Davis

Collaborators

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Publications

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Stillmaker A, Bohnenstiehl B, Stillmaker L, et al. (2020) Scalable energy-efficient parallel sorting on a fine-grained many-core processor array Journal of Parallel and Distributed Computing. 138: 32-47
Bohnenstiehl B, Stillmaker A, Pimentel J, et al. (2017) KiloCore: A Fine-Grained 1,000-Processor Array for Task-Parallel Applications Ieee Micro. 37: 63-69
Bohnenstiehl B, Stillmaker A, Pimentel JJ, et al. (2017) KiloCore: A 32-nm 1000-Processor Computational Array Ieee Journal of Solid-State Circuits. 52: 891-902
Stillmaker A, Baas BM. (2017) Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm Integration. 58: 74-81
Pimentel JJ, Bohnenstiehl B, Baas BM. (2016) Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs Ieee Transactions On Very Large Scale Integration (Vlsi) Systems
Liu B, Foroozannejad MH, Ghiasi S, et al. (2015) Optimizing power of many-core systems by exploiting dynamic voltage, frequency and core scaling Midwest Symposium On Circuits and Systems. 2015
Liu B, Bohnenstiehl B, Baas BM. (2015) Scalable hardware-based power management for many-core systems Conference Record - Asilomar Conference On Signals, Systems and Computers. 2015: 1834-1838
Pimentel JJ, Baas BM. (2015) Hybrid floating-point modules with low area overhead on a fine-grained processing core Conference Record - Asilomar Conference On Signals, Systems and Computers. 2015: 1829-1833
Tran AT, Baas BM. (2014) Achieving high-performance on-chip networks with shared-buffer routers Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 1391-1403
Xiao Z, Baas BM. (2014) Processor tile shapes and interconnect topologies for dense on-chip networks Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 22: 1377-1390
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