Farzan Farbiz, Ph.D.
Affiliations: | 2010 | University of Illinois, Urbana-Champaign, Urbana-Champaign, IL |
Area:
Electronics and Electrical EngineeringGoogle:
"Farzan Farbiz"Parents
Sign in to add mentor| Elyse Rosenbaum | grad student | 2010 | UIUC | |
| (Modeling and suppression of latchup.) | ||||
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Publications
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| Farbiz F, Rosenbaum E. (2011) Modeling and understanding of external latchup in CMOS technologies-part II: Minority carrier collection efficiency Ieee Transactions On Device and Materials Reliability. 11: 426-432 |
| Farbiz F, Rosenbaum E. (2011) Modeling and understanding of external latchup in CMOS technologies-part I: Modeling latchup trigger current Ieee Transactions On Device and Materials Reliability. 11: 417-425 |
| Farbiz F, Rosenbaum E. (2010) Understanding transient latchup hazards and the impact of guard rings Ieee International Reliability Physics Symposium Proceedings. 466-473 |
| Farbiz F, Rosenbaum E. (2009) A new compact model for external latchup Microelectronics Reliability. 49: 1447-1454 |
| Farbiz F, Rosenbaum E. (2008) Modeling of majority and minority carrier triggered external latchup Ieee International Reliability Physics Symposium Proceedings. 270-277 |
| Farbiz F, Rosenbaum E. (2008) Guard ring interactions and their effect on CMOS latchup resilience Technical Digest - International Electron Devices Meeting, Iedm |
| Farbiz F, Rosenbaum E. (2007) An investigation of external latchup Annual Proceedings - Reliability Physics (Symposium). 600-601 |
| Farbiz F, Rosenbaum E. (2007) Analytical modeling of external latchup Electrical Overstress/Electrostatic Discharge Symposium Proceedings |
| Taherzadeh-S M, Amelifard B, Iman-Eini H, et al. (2003) Power and delay estimation of CMOS inverters using fully analytical approach 2003 Southwest Symposium On Mixed-Signal Design, Ssmsd 2003. 116-120 |