Nuttorn Jangkrajarng, Ph.D.
Affiliations: | 2006 | University of Washington, Seattle, Seattle, WA |
Area:
Electronics and Electrical EngineeringGoogle:
"Nuttorn Jangkrajarng"Parents
Sign in to add mentor| Chuan-Jin Richard Shi | grad student | 2006 | University of Washington (Computer Science Tree) | |
| (Analog/RF VLSI layout generation: Layout retargeting via symbolic template.) | ||||
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Publications
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| Zhou L, Wakayama C, Panda R, et al. (2007) Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits 2007 Ieee International Conference On Computer Design, Iccd 2007. 194-201 |
| Bhattacharya S, Jangkrajarng N. (2006) Multilevel symmetry-constraint generation for retargeting large analog layouts Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 945-960 |
| Jangkrajarng N, Zhang L, Bhattacharya S, et al. (2006) Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts Ieee/Acm International Conference On Computer-Aided Design, Digest of Technical Papers, Iccad. 342-348 |
| Zhou L, Wakayama C, Jangkrajarng N, et al. (2006) A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 2006: 92-93 |
| Hartono R, Jangkrajarng N, Bhattacharya S, et al. (2005) Automatic device layout generation for analog layout retargeting Proceedings of the Ieee International Conference On Vlsi Design. 457-462 |
| Bhattacharya S, Jangkrajarng N, Richard Shi CJ. (2005) Template-driven parasitic-aware optimization of analog integrated circuit layouts Proceedings - Design Automation Conference. 644-647 |
| Bhattacharya S, Jangkrajarng N, Hartono R, et al. (2004) Correct-by-construction layout-centric retargeting of large analog designs Proceedings - Design Automation Conference. 139-144 |
| Jangkrajarng N, Bhattacharya S, Hartono R, et al. (2004) Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 394-399 |
| Bhattacharya S, Jangkrajarng N, Hartono R, et al. (2004) Hierarchical extraction and verification of symmetry constraints for analog layout automation Proceedings of the Asia and South Pacific Design Automation Conference, Asp-Dac. 400-405 |
| Jangkrajarng N, Bhattacharya S, Hartono R, et al. (2003) IPRAIL - Intellectual property reuse-based analog IC layout automation Integration, the Vlsi Journal. 36: 237-262 |