Chien-In H. Chen
Affiliations: | Wright State University, Fairborn, OH, United States |
Area:
Electronics and Electrical EngineeringGoogle:
"Chien-In Chen"
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Publications
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| Benson S, Chen CH, Lin DM, et al. (2016) Digital linear chirp receiver for high chirp rates with high resolution time-of-arrival and time-of-departure estimation Ieee Transactions On Aerospace and Electronic Systems. 52: 1146-1154 |
| Chen J, Chen CH. (2015) Process Variation Aware Wide Tuning Band Pass Filter for Steep Roll-Off High Rejection Vlsi Design. 2015: 1-9 |
| Yelamarthi K, Chen CH. (2012) Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations Ieee Transactions On Semiconductor Manufacturing. 25: 255-265 |
| George K, Chen CH. (2011) A Hybrid Computing Platform Digital Wideband Receiver Design and Performance Measurement Ieee Transactions On Instrumentation and Measurement. 60: 3956-3958 |
| Lee Y-G, Chen CH. (2009) Dynamic Kernel Function Fast Fourier Transform With Variable Truncation Scheme for Wideband Coarse Frequency Detection Ieee Transactions On Instrumentation and Measurement. 58: 1555-1562 |
| Yelamarthi K, Chen CH. (2008) Process Variation Aware Transistor Sizing for Load Balance of Multiple Paths in Dynamic CMOS for Timing Optimization Journal of Computers. 3: 21-28 |
| Wang M, Chen CH, Radhakrishnan S. (2007) Low-Power 4-b 2.5-GSPS Pipelined Flash Analog-to-Digital Converter in 130-nm CMOS Ieee Transactions On Instrumentation and Measurement. 56: 1064-1073 |
| Chen CH, Wagh M. (2002) Testability Synthesis for Jumping Carry Adders Vlsi Design. 2002: 155-169 |
| Huang JA, Chen CH. (2002) Timing-Driven-Testable Convergent Tree Adders Vlsi Design. 2002: 637-645 |
| Chen CH, Kumar A. (1994) Comments on "Area-time optimal adder design" Ieee Transactions On Computers. 43: 507-512 |