Satyanand Nalam, Ph.D.
Affiliations: | 2011 | University of Virginia, Charlottesville, VA |
Area:
Electronics and Electrical EngineeringGoogle:
"Satyanand Nalam"Parents
Sign in to add mentor| Benton H. Calhoun | grad student | 2011 | UVA | |
| (Circuit and CAD Solutions for Optimal SRAM Design in Nanoscale CMOS.) | ||||
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Publications
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| Guo Z, Kim D, Nalam S, et al. (2019) A 23.6-Mb/mm $^{2}$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications Ieee Journal of Solid-State Circuits. 54: 210-216 |
| Kulkarni JP, Keane J, Koo KH, et al. (2016) 5.6 Mb/mm² 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology Ieee Journal of Solid-State Circuits |
| Karl E, Guo Z, Conary J, et al. (2015) A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry Ieee Journal of Solid-State Circuits |
| Nalam S, Calhoun BH. (2011) 5T SRAM With Asymmetric Sizing for Improved Read Stability Ieee Journal of Solid-State Circuits. 46: 2431-2442 |
| Mann RW, Wang J, Nalam S, et al. (2010) Impact of circuit assist methods on margin and performance in 6T SRAM Solid-State Electronics. 54: 1398-1407 |