Andreas Veneris
Affiliations: | Electrical and Computer Engineering | University of Toronto, Toronto, ON, Canada |
Area:
Electronics and Electrical EngineeringGoogle:
"Andreas Veneris"
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Publications
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| Poulos Z, Veneris A. (2018) Failure Triage in RTL Regression Verification Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1893-1906 |
| Berryhill R, Veneris A. (2018) Methodologies for Diagnosis of Unreachable States via Property Directed Reachability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1298-1311 |
| Adler J, Veneris A. (2017) Leveraging Software Configuration Management in Automated RTL Design Debug Ieee Design & Test of Computers. 34: 47-53 |
| Poulos Z, Veneris A. (2016) Exemplar-based Failure Triage for Regression Design Debugging Journal of Electronic Testing. 32: 125-136 |
| Mangassarian H, Le B, Veneris A. (2014) Debugging RTL Using Structural Dominance Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 153-166 |
| Keng B, Veneris A. (2013) Path-Directed Abstraction and Refinement for SAT-Based Design Debugging Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1609-1622 |
| Yang Y, Veneris A, Nicolici N. (2012) Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment Ieee Transactions On Very Large Scale Integration Systems. 20: 1118-1131 |
| Mangassarian H, Veneris A, Najm FN. (2012) Maximum circuit activity estimation using pseudo-Boolean satisfiability Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 271-284 |
| Safi E, Moshovos A, Veneris A. (2011) Two-stage, pipelined register renaming Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 19: 1926-1931 |
| Yang YS, Sinha S, Veneris A, et al. (2011) Automating logic transformations with approximate SPFDs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 651-664 |