Parents
Sign in to add mentor| Sung Kyu Lim | grad student | 2012 | Georgia Tech | |
| (Through-silicon-via-aware prediction and physical design for multi-granularity 3D integrated circuits.) | ||||
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Publications
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| Musavvir S, Chatterjee A, Kim RG, et al. (2020) Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration Ieee Transactions On Very Large Scale Integration Systems. 28: 686-699 |
| Chaudhuri A, Banerjee S, Park H, et al. (2020) Advances in Design and Test of Monolithic 3-D ICs Ieee Design & Test of Computers. 37: 92-100 |
| Kim D, Hsu S, Milor L. (2019) Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown Ieee Transactions On Very Large Scale Integration Systems. 27: 1640-1651 |
| Lin SD, Kim DH. (2019) Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs Ieee Transactions On Emerging Topics in Computing. 7: 301-310 |
| Long Y, Kim D, Lee E, et al. (2019) A Ferroelectric FET-Based Processing-in-Memory Architecture for DNN Acceleration Ieee Journal On Exploratory Solid-State Computational Devices and Circuits. 5: 113-122 |
| Lee D, Das S, Kim DH, et al. (2018) Design Space Exploration of 3D Network-on-Chip Acm Journal On Emerging Technologies in Computing Systems. 14: 1-26 |
| Hong I, Kim DH. (2018) Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 1614-1626 |
| Lin SD, Kim DH. (2018) Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 845-854 |
| Kim D, Milor L. (2017) An ECC-Assisted Postpackage Repair Methodology in Main Memory Systems Ieee Transactions On Very Large Scale Integration Systems. 25: 2045-2058 |
| Kim DH, Lim SK. (2016) Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools-Part 2 Ieee Design and Test. 33: 7-8 |