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| Luo G, Xiong G, Huang X, et al. (2023) Geometry Sampling-Based Adaption to DCGAN for 3D Face Generation. Sensors (Basel, Switzerland). 23 |
| Kim DH, Athikulwongse K, Healy MB, et al. (2015) Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory) Ieee Transactions On Computers. 64: 112-125 |
| Zhao X, Scheuermann MR, Lim SK. (2014) Analysis and modeling of dc current crowding for tsv-based 3-d connections and power integrity Ieee Transactions On Components, Packaging and Manufacturing Technology. 4: 123-133 |
| Chae K, Zhao X, Lim SK, et al. (2013) Tier Adaptive Body Biasing: A Post-Silicon Tuning Method to Minimize Clock Skew Variations in 3-D ICs Ieee Transactions On Components, Packaging and Manufacturing Technology. 3: 1720-1730 |
| Zhao X, Tolbert JR, Mukhopadhyay S, et al. (2012) Variation-Aware Clock Network Design Methodology for Ultralow Voltage (ULV) Circuits Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1222-1234 |
| Zhao X, Minz J, Lim SK. (2011) Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs Ieee Transactions On Components, Packaging and Manufacturing Technology. 1: 247-259 |
| Zhao X, Lewis DL, Lee HHS, et al. (2011) Low-power clock tree design for pre-bond testing of 3-D stacked ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 732-745 |