Shreepad Panth

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2015 Georgia Institute of Technology, Atlanta, GA 
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"Shreepad Panth"
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Panth S, Samal SK, Samadi K, et al. (2017) Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1265-1273
Panth S, Samadi K, Du Y, et al. (2017) Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 1716-1724
Yu YS, Panth S, Lim SK. (2016) Electrical Coupling of Monolithic 3-D Inverters Ieee Transactions On Electron Devices
Samal SK, Panth S, Samadi K, et al. (2016) Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1707-1720
Noia B, Panth S, Chakrabarty K, et al. (2015) Scan test of die logic in 3-D ICs using TSV probing Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 23: 317-330
Ceyhan A, Jung M, Panth S, et al. (2015) Evaluating Chip-Level Impact of Cu/Low-κ Performance Degradation on Circuit Performance at Future Technology Nodes Ieee Transactions On Electron Devices
Panth S, Samadi K, Du Y, et al. (2015) Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 540-553
Kim DH, Athikulwongse K, Healy MB, et al. (2015) Design and analysis of 3D-MAPS (3D Massively parallel processor with stacked memory) Ieee Transactions On Computers. 64: 112-125
Panth S, Samal SK, Yu YS, et al. (2014) Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs Journal of Information and Communication Convergence Engineering. 12: 186-192
Lee J, Nicopoulos C, Lee HG, et al. (2013) IsoNet: Hardware-Based Job Queue Management for Many-Core Architectures Ieee Transactions On Very Large Scale Integration Systems. 21: 1080-1093
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