Anand Rajaram

Affiliations: 
2008 University of Texas at Austin, Austin, Texas, U.S.A. 
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"Anand Rajaram"
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Rajaram A, Pan DZ. (2011) Robust Chip-Level Clock Tree Synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 30: 877-890
Rajaram A, Pan DZ. (2010) MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 29: 1945-1958
Rajagopal A, Rajaram A, Damodaran R, et al. (2008) Context analysis and validation of lithography induced systematic variations in 65nm designs Proceedings of Spie - the International Society For Optical Engineering. 6925
Pan DZ, Yu P, Cho M, et al. (2008) Design for manufacturing meets advanced process control: A survey Journal of Process Control. 18: 975-984
Rajaram A, Hu J, Mahapatra R. (2006) Reducing clock skew variability via crosslinks Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 25: 1176-1182
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