Subhendu Roy
Affiliations: | 2015 | University of Texas at Austin, Austin, Texas, U.S.A. |
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"Subhendu Roy"
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Publications
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Ma Y, Roy S, Miao J, et al. (2019) Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 2298-2311 |
Miao J, Li M, Roy S, et al. (2018) SD-PUF: Spliced Digital Physical Unclonable Function Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 927-940 |
Roy S, Liu D, Singh J, et al. (2016) OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations under Multiple Operating Conditions Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1618-1629 |
Roy S, Choudhury M, Puri R, et al. (2016) Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 820-831 |
Yu B, Xu X, Roy S, et al. (2016) Design for manufacturability and reliability in extreme-scaling VLSI Science China Information Sciences. 1-23 |
Roy S, Mattheakis PM, Masse-Navette L, et al. (2015) Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 589-602 |
Yu B, Roy S, Gao J, et al. (2014) Triple patterning lithography layout decomposition using end-cutting Journal of Micro-Nanolithography Mems and Moems. 14: 11002-11002 |
Roy S, Choudhury M, Puri R, et al. (2014) Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 1517-1530 |