Year |
Citation |
Score |
2021 |
Jiang W, Xiong J, Shi Y. A co-design framework of neural networks and quantum circuits towards quantum advantage. Nature Communications. 12: 579. PMID 33495480 DOI: 10.1038/s41467-020-20729-5 |
0.395 |
|
2020 |
Tida UR, Zhuo C, Liu L, Shi Y. Dynamic Frequency Scaling Aware Opportunistic Through-Silicon-Via Inductor Utilization in Resonant Clocking Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 39: 281-293. DOI: 10.1109/Tcad.2018.2887053 |
0.349 |
|
2019 |
Xu X, Zhang X, Yu B, Hu XS, Rowen C, Hu J, Shi Y. DAC-SDC Low Power Object Detection Challenge for UAV Applications. Ieee Transactions On Pattern Analysis and Machine Intelligence. PMID 31395535 DOI: 10.1109/Tpami.2019.2932429 |
0.316 |
|
2019 |
Tida UR, Zhuo C, Shi Y. Single-Inductor–Multiple-Tier Regulation: TSV-Inductor-Based On-Chip Buck Converters for 3-D IC Power Delivery Ieee Transactions On Very Large Scale Integration Systems. 27: 2305-2316. DOI: 10.1109/Tvlsi.2019.2919606 |
0.353 |
|
2019 |
Liu L, Wang Q, Zhu W, Mo H, Wang T, Yin S, Shi Y, Wei S. A Face Alignment Accelerator Based on Optimized Coarse-to-Fine Shape Searching Ieee Transactions On Circuits and Systems For Video Technology. 29: 2467-2481. DOI: 10.1109/Tcsvt.2018.2867499 |
0.359 |
|
2019 |
Zhuo C, Unda K, Shi Y, Shih W. From Layout to System: Early Stage Power Delivery and Architecture Co-Exploration Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 1291-1304. DOI: 10.1109/Tcad.2018.2834438 |
0.309 |
|
2019 |
Xu X, Lin F, Xu W, Yao X, Shi Y, Zeng D, Hu Y. MDA: A Reconfigurable Memristor-Based Distance Accelerator for Time Series Mining on Data Centers Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 785-797. DOI: 10.1109/Tcad.2018.2834431 |
0.367 |
|
2019 |
Zhang GL, Li B, Shi Y, Hu J, Schlichtmann U. EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration Under Process Variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 38: 705-718. DOI: 10.1109/Tcad.2018.2818713 |
0.368 |
|
2019 |
Li D, Xu X, Liu L, Zhang L, Zhuo C, Shi Y. Optimal design of a low-power, phase-switching modulator for implantable medical applications Integration. 69: 289-300. DOI: 10.1016/J.Vlsi.2019.02.003 |
0.348 |
|
2018 |
Liu Z, Luo S, Xu X, Shi Y, Zhuo C. A Multi-Level-Optimization Framework for FPGA-Based Cellular Neural Network Implementation Acm Journal On Emerging Technologies in Computing Systems. 14: 47. DOI: 10.1145/3273957 |
0.373 |
|
2018 |
Xu X, Lu Q, Wang T, Hu Y, Zhuo C, Liu J, Shi Y. Efficient Hardware Implementation of Cellular Neural Networks with Incremental Quantization and Early Exit Acm Journal On Emerging Technologies in Computing Systems. 14: 1-20. DOI: 10.1145/3264817 |
0.377 |
|
2018 |
Schulze TE, Beetner DG, Shi Y, Kwiat KA, Kamhoua CA. Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding Ieee Transactions On Very Large Scale Integration Systems. 26: 2007-2015. DOI: 10.1109/Tvlsi.2018.2844180 |
0.359 |
|
2018 |
Xu X, Lin F, Wang A, Yao X, Lu Q, Xu W, Shi Y, Hu Y. Accelerating Dynamic Time Warping With Memristor-Based Customized Fabrics Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 729-741. DOI: 10.1109/Tcad.2017.2729344 |
0.369 |
|
2018 |
Geng H, Kwiat KA, Kamhoua CA, Shi Y. On Random Dynamic Voltage Scaling for Internet-of-Things: A Game-Theoretic Approach Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 123-132. DOI: 10.1109/Tcad.2017.2717780 |
0.336 |
|
2018 |
Zhang GL, Li B, Liu J, Shi Y, Schlichtmann U. Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 392-405. DOI: 10.1109/Tcad.2017.2702632 |
0.374 |
|
2018 |
Li Y, Dhwaj K, Wong C, Du Y, Du L, Tang Y, Shi Y, Itoh T, Chang MF. A Novel Fully Synthesizable All-Digital RF Transmitter for IoT Applications Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 37: 146-158. DOI: 10.1109/Tcad.2017.2684097 |
0.326 |
|
2018 |
Chen B, Zhuo C, Shi Y. A physics-aware methodology for equivalent circuit model extraction of TSV-inductors Integration. 63: 160-166. DOI: 10.1016/J.Vlsi.2018.07.002 |
0.372 |
|
2017 |
Al-jabery K, Xu Z, Yu W, Wunsch DC, Xiong J, Shi Y. Demand-Side Management of Domestic Electric Water Heaters Using Approximate Dynamic Programming Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 36: 775-788. DOI: 10.1109/Tcad.2016.2598563 |
0.451 |
|
2017 |
Wu P, Mak W, Wang T, Zhuo C, Unda K, Shi Y. A routing framework for technology migration with bump encroachment Integration. 58: 1-8. DOI: 10.1016/J.Vlsi.2017.01.003 |
0.369 |
|
2016 |
Wang T, Zhang C, Xiong J, Luo PW, Cheng LC, Shi Y. On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 35: 1744-1754. DOI: 10.1109/Tcad.2015.2513007 |
0.504 |
|
2016 |
Geng H, Liu J, Luo PW, Cheng LC, Grant SL, Shi Y. Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling Integration, the Vlsi Journal. DOI: 10.1016/J.Vlsi.2016.05.007 |
0.398 |
|
2015 |
Wu J, Xiong J, Shi Y. Efficient Location Identification of Multiple Line Outages With Limited PMUs in Smart Grids Ieee Transactions On Power Systems. 30: 1659-1668. DOI: 10.1109/Tpwrs.2014.2357751 |
0.484 |
|
2015 |
Zhang C, Yu W, Wang Q, Shi Y. Fast Random Walk Based Capacitance Extraction for the 3-D IC Structures With Cylindrical Inter-Tier-Vias Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 1977-1990. DOI: 10.1109/Tcad.2015.2440323 |
0.361 |
|
2015 |
Geng H, Liu J, Luo PW, Cheng LC, Grant SL, Shi Y. Selective body biasing for post-silicon tuning of sub-threshold designs: An adaptive filtering approach Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 713-725. DOI: 10.1109/Tcad.2015.2401552 |
0.369 |
|
2015 |
Chen YG, Wen WY, Shi Y, Hon WK, Chang SC. Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 34: 577-588. DOI: 10.1109/Tcad.2014.2385759 |
0.356 |
|
2014 |
Wu C, Shi Y, Kar S. Exploring demand flexibility in heterogeneous aggregators: An LMP-based pricing scheme Acm Transactions in Embedded Computing Systems. 13: 57. DOI: 10.1145/2544375.2544377 |
0.32 |
|
2014 |
Tida UR, Yang R, Zhuo C, Shi Y. On the Efficacy of Through-Silicon-Via Inductors Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. DOI: 10.1109/Tvlsi.2014.2338862 |
0.373 |
|
2014 |
Zhang C, Ma D, Li C, Shi Y. Runtime Self-Calibrated Temperature–Stress Cosensor for 3-D Integrated Circuits Ieee Transactions On Very Large Scale Integration Systems. 22: 2411-2417. DOI: 10.1109/Tvlsi.2013.2290132 |
0.314 |
|
2014 |
Chen YG, Geng H, Lai KY, Shi Y, Chang SC. Multibit retention registers for power gated designs: Concept, design, and deployment Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 507-518. DOI: 10.1109/Tcad.2013.2293881 |
0.335 |
|
2014 |
Wang T, Zhang C, Xiong J, Shi Y. On the Deployment of On-Chip Noise Sensors Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 33: 519-531. DOI: 10.1109/Tcad.2013.2293477 |
0.502 |
|
2014 |
Gong F, Shi Y, Yu H, He L. Variability-aware parametric yield estimation for analog/mixed-signal circuits: Concepts, algorithms, and challenges Ieee Design and Test. 31: 6-15. DOI: 10.1109/Mdat.2014.2299279 |
0.595 |
|
2013 |
Shi Y, Xiong J, Zolotov V, Visweswariah C. Order statistics for correlated random variables and its application to at-speed testing Acm Transactions On Design Automation of Electronic Systems. 18: 42. DOI: 10.1145/2491477.2491486 |
0.498 |
|
2013 |
Lung C, Su Y, Huang H, Shi Y, Chang S. Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 1100-1109. DOI: 10.1109/Tcad.2013.2245375 |
0.329 |
|
2013 |
Luo G, Shi Y, Cong J. An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 32: 510-523. DOI: 10.1109/Tcad.2012.2232708 |
0.519 |
|
2012 |
Yao W, Shi Y, He L, Pamarti S. Worst-Case Estimation for Data-Dependent Timing Jitter and Amplitude Noise in High-Speed Differential Link Ieee Transactions On Very Large Scale Integration Systems. 20: 89-97. DOI: 10.1109/Tvlsi.2010.2090544 |
0.553 |
|
2012 |
Wu J, Shi Y, Choi M. Measurement and Evaluation of Power Analysis Attacks on Asynchronous S-Box Ieee Transactions On Instrumentation and Measurement. 61: 2765-2775. DOI: 10.1109/Tim.2012.2200399 |
0.335 |
|
2012 |
Lee M, Shi Y, Chang S. Efficient Wakeup Scheduling Considering Both Resource Usage and Timing Budget for Power Gating Designs Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 31: 1041-1049. DOI: 10.1109/Tcad.2012.2187205 |
0.382 |
|
2011 |
Shi Y, Xiong J, Chen H, He L. Runtime Resonance Noise Reduction with Current Prediction Enabled Frequency Actuator Ieee Transactions On Very Large Scale Integration Systems. 19: 508-512. DOI: 10.1109/Tvlsi.2009.2036266 |
0.541 |
|
2010 |
Yu H, Chu C, Shi Y, Smart D, He L, Tan SX-. Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling Ieee Transactions On Very Large Scale Integration Systems. 18: 1399-1411. DOI: 10.1109/Tvlsi.2009.2024343 |
0.432 |
|
2010 |
Shi Y, He L. EMPIRE: An Efficient and Compact Multiple-Parameterized Model-Order Reduction Method for Physical Optimization Ieee Transactions On Very Large Scale Integration Systems. 18: 108-118. DOI: 10.1109/Tvlsi.2008.2007842 |
0.446 |
|
2008 |
Shi Y, Xiong J, Liu C, He L. Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 27: 1253-1263. DOI: 10.1109/Tcad.2008.923636 |
0.482 |
|
2007 |
Shi Y, Mesa P, Yu H, He L. Circuit-simulated obstacle-aware Steiner routing Acm Transactions On Design Automation of Electronic Systems. 12: 28. DOI: 10.1145/1255456.1255465 |
0.436 |
|
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