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Seema B. Anand, Ph.D. - Publications

Affiliations: 
2001 University of California, Los Angeles, Los Angeles, CA 
Area:
Analog, RF, mixed-signal integrated circuit design, dual-standard RF transceivers, phase-locked systems and frequency synthesizers, A/D and D/A converters, high-speed data communication circuits
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12 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2014 Conta M, Rodal E, Anand S, Jensen H, Huang H, Lin YW, Liu Z, De Flaviis F, Benboudjema K. A 0.9dB NF 9mW 28nm triple-band GNSS radio receiver Digest of Papers - Ieee Radio Frequency Integrated Circuits Symposium. 213-216. DOI: 10.1109/RFIC.2014.6851701  0.377
2010 Lee CP, Behzad A, Marholev B, Magoon V, Bhatti I, Li D, Bothra S, Afsahi A, Ojo D, Roufoogaran R, Li T, Chang Y, Rao KR, Au S, Seetharam P, ... ... Anand S, et al. A multistandard, multiband SoC with integrated BT, FM, WLAN radios and integrated power amplifier Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 454-455. DOI: 10.1109/ISSCC.2010.5433962  0.49
2008 Afsahi A, Rael JJ, Behzad A, Chien HM, Pan M, Au S, Ojo A, Lee CP, Anand SB, Chien K, Wu S, Roufoogaran R, Zolfaghari A, Leete JC, Tran L, et al. A low-power single-weight-combiner 802.11abg SoC in 0.13 μm CMOS for embedded applications utilizing an area and power efficient Cartesian phase shifter and mixer circuit Ieee Journal of Solid-State Circuits. 43: 1101-1114. DOI: 10.1109/JSSC.2008.920338  0.539
2007 Marholev B, Pan M, Chien E, Zhang L, Roufoogaran R, Wu S, Bhatti I, Lin TH, Kappes M, Khorram S, Anand S, Zolfaghari A, Castaneda J, Chien CM, Ibrahim B, et al. A single-chip bluetooth EDR device in 0.13μm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 558-559+621+557. DOI: 10.1109/ISSCC.2007.373542  0.522
2005 Khorram S, Darabi H, Zhou Z, Li Q, Marholev B, Chiu J, Castaneda J, Chien HM, Anand SB, Wu S, Pan MA, Roofougaran R, Kim HJ, Lettieri P, Ibrahim B, et al. A fully integrated SOC for 802.11b in 0.18-μm CMOS Ieee Journal of Solid-State Circuits. 40: 2492-2499. DOI: 10.1109/JSSC.2005.857419  0.497
2005 Darabi H, Khorram S, Zhou Z, Li T, Marholev B, Chiu J, Castaneda J, Chien E, Anand S, Wu S, Pan M, Roufoogaran R, Kim H, Lettieri P, Ibrahim B, et al. A fully integrated SoC for 802.11b in 0.18μm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 48: 66-67+530.  0.443
2005 Darabi H, Khorram S, Zhou Z, Li T, Marholev B, Chiu J, Castaneda J, Chien E, Anand S, Wu S, Pan M, Roufoogaran R, Kim H, Lettieri P, Ibrahim B, et al. A fully integrated SoC for 802.11b in 0.18μm CMOS Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 48: 66-67+530.  0.443
2004 Behzad A, Lin E, Carter K, Kappes M, Shi ZM, Lin L, Wu S, Anand S, Nguyen T, Yuan D, Wong YC, Fong V, Yeung B, Rofougaran A. A 4.92-5.845GHz direct-conversion CMOS transceiver for IEEE 802.11a wireless LAN Ieee Radio Frequency Integrated Circuits Symposium, Rfic, Digest of Technical Papers. 335-338.  0.486
2003 Behzad AR, Shi ZM, Anand SB, Lin L, Carter KA, Kappes MS, Lin TH, Nguyen T, Yuan D, Wu S, Wong YC, Fong V, Rofougaran A. A 5-GHz Direct-Conversion CMOS Transceiver Utilizing Automatic Frequency Control for the IEEE 802.11a Wireless LAN Standard Ieee Journal of Solid-State Circuits. 38: 2209-2220. DOI: 10.1109/Jssc.2003.819085  0.499
2003 Behzad A, Lin L, Shi ZM, Anand S, Carter K, Kappes M, Lin E, Nguyen T, Yuan D, Wu S, Wong YC, Fong V, Rofougaran A. Direct-conversion CMOS transceiver with automatic frequency control for 802.11a wireless LANs Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 349+356-357+498.  0.401
2001 Anand SB, Razavi B. A CMOS clock recovery circuit for 2.5-Gb/s NRZ data Ieee Journal of Solid-State Circuits. 36: 432-439. DOI: 10.1109/4.910482  0.499
2000 Anand SB, Razavi B. 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-μm CMOS technology Proceedings of the Custom Integrated Circuits Conference. 379-382.  0.451
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