Charles Zukowski - Publications

Affiliations: 
Electrical Engineering Columbia University, New York, NY 

57 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any innacuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2010 Irez K, Hu J, Zukowski CA. Characteristics of MS-CMOS logic in sub-32nm technologies Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 393-396. DOI: 10.1145/1785481.1785572  1
2006 Huang TCD, Zukowski CA. Reconfigurable digital/analog processor array for the simulation of gene regulatory networks Midwest Symposium On Circuits and Systems. 1: 552-556. DOI: 10.1109/MWSCAS.2006.382122  1
2006 Bastani A, Zukowski CA. A low-leakage high-speed monotonic static CMOS 64b adder in a dual gate oxide 65-nm CMOS technology Proceedings - International Symposium On Quality Electronic Design, Isqed. 312-317. DOI: 10.1109/ISQED.2006.12  1
2006 Bastani A, Zukowski CA. Monotonic static CMOS tradeoffs in sub-100nm technologies Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 2006: 278-283.  1
2005 Chin P, Zukowski CA, Gristede GD, Kosonocky SV. Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies Integration, the Vlsi Journal. 38: 491-504. DOI: 10.1016/j.vlsi.2004.07.011  1
2005 Bastani A, Zukowski CA. Characterization of monotonic static CMOS gates in a 65nm technology Proceedings of the Acm Great Lakes Symposium On Vlsi, Glsvlsi. 408-411.  1
2004 Bastani A, Zukowski CA. Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage Proceedings of the Acm Great Lakes Symposium On Vlsi. 119-122.  1
2004 Chin P, Zukowski CA, Gristede GD, Kosonocky S. Characterization of logic circuit techniques for high leakage CMOS technologies Proceedings of the Acm Great Lakes Symposium On Vlsi. 230-235.  1
2004 Garrett D, Zukowski C, Lach J. Proceedings of the ACM Great Lakes Symposium on VLSI: Foreword Proceedings of the Acm Great Lakes Symposium On Vlsi. iii.  1
2003 Tagkopoulos I, Zukowski C, Cavelier G, Anastassiou D. A custom FPGA for the simulation of gene regulatory networks Proceedings of the Ieee Great Lakes Symposium On Vlsi. 132-135.  1
2000 Renshaw AA, Reibel JH, Zukowski CA, Penn K, McClintock RO, Friedman MB. An assessment of on-line engineering design problem presentation strategies Ieee Transactions On Education. 43: 83-91. DOI: 10.1109/13.848058  1
2000 Wang SY, Zukowski CA. Energy reduction from using selective precharge in two different logic arrays Midwest Symposium On Circuits and Systems. 1: 84-87.  1
2000 Abbasi NA, Zukowski CA. Trading system performance for energy use in a VLSI implementation of an adaptive equalizer Midwest Symposium On Circuits and Systems. 2: 544-547.  1
2000 Li SH, Zukowski CA. Application of dynamic power supply scaling in a low-energy ATM interface Proceedings - Ieee International Symposium On Circuits and Systems. 5: V-745-V-748.  1
2000 Dare GL, Zukowski CA. Accuracy management for mixed-mode digital VLSI simulation Proceedings of the Ieee Great Lakes Symposium On Vlsi. 167-170.  1
1999 Tretz C, Chuang CT, Terman L, Anderson C, Pelella M, Zukowski C. Metastability of SOI CMOS latches International Journal of Electronics. 86: 807-813.  1
1999 Wang SY, Zukowski CA. Analysis of the logic model used in selective precharge Midwest Symposium On Circuits and Systems. 1: 88-91.  1
1998 Gristede GD, Ruehli AE, Zukowski CA. Convergence properties of waveform relaxation circuit simulation methods Ieee Transactions On Circuits and Systems I: Fundamental Theory and Applications. 45: 726-738. DOI: 10.1109/81.703839  1
1998 Tretz C, Chuang CT, Terman L, Pelella M, Zukowski C. Performance comparison of differential static CMOS circuit topologies in SOI technology Ieee International Soi Conference. 123-124.  1
1997 Tretz C, Chuang CT, Terman LM, Anderson CJ, Zukowski C. Metastability of SOI CMOS latches Ieee International Soi Conference. 162-163.  1
1997 Li SH, Zukowski CA. Self-timed Cyclic Redundancy Check (CRC) in VLSI Midwest Symposium On Circuits and Systems. 2: 1021-1023.  1
1997 Zukowski CA, Wang SY. Use of selective precharge for low-power content-addressable memories Proceedings - Ieee International Symposium On Circuits and Systems. 3: 1788-1791.  1
1997 Zukowski CA, Wang SY. Use of selective precharge for low-power on the match lines of content-addressable memories Records of the Ieee International Workshop On Memory Technology, Design and Testing. 64-68.  1
1997 Zukowski CA, Wang SY. Power reduction in large fan-in CMOS gates in logic arrays using selective precharge Proceedings of the Ieee Great Lakes Symposium On Vlsi. 83-87.  1
1996 Tretz C, Zukowski C. Conservative modeling of the contribution of spurious transitions to power dissipation in digital CMOS VLSI circuits Midwest Symposium On Circuits and Systems. 1: 317-320.  1
1996 Tretz C, Ranganathan S, Zukowski C. Comparison of a wide range of differential CMOS logic topologies Midwest Symposium On Circuits and Systems. 1: 179-182.  1
1996 Tretz C, Zukowski C. CMOS transistor sizing for minimization of energy-delay product Proceedings of the Ieee Great Lakes Symposium On Vlsi. 168-173.  1
1996 Shi H, Zukowski C, Wing O. VLSI design optimization of input/output-buffered broadband ATM switches Proceedings - Ieee Infocom. 2: 810-817.  1
1995 Shi H, Abbasi N, Zukowski C, Wing O. Buffer size trade-offs in input/output-buffered ATM switches under various conditions Proceedings of the International Conference On Computer Communications and Networks, Icccn. 258-263.  1
1994 Zukowski C. High-Frequency Pattern Generation using Multiple Input Channels and Combinational Logic Ieee Transactions On Circuits and Systems Ii: Analog and Digital Signal Processing. 41: 467-471. DOI: 10.1109/82.298379  1
1994 Shi H, Ennis D, Fernandez S, Zukowski C, Wing O. VLSI design and cost analysis of broadband ATM switch elements Proceedings of the Annual Ieee International Asic Conference and Exhibit. 331-336.  1
1994 Landsberg P, Zukowski C. Generic queue scheduling: concepts and VLSI Proceedings - Ieee Infocom. 3: 1438-1445.  1
1994 Bai YW, Zukowski CA. Delay-time bounds and waveform bounds for RLCG ladder networks Proceedings of the Ieee Annual Simulation Symposium. 23-30.  1
1993 Chen DP, Zukowski C, Banu M. Macromodeling BicMOS gates for circuit optimization Proceedings of the Custom Integrated Circuits Conference. 8.1.1-8.1.4.  1
1993 Lin PS, Zukowski CA. Analysis and control of timing jitter in digital logic arising from noise voltage sources Proceedings - Ieee International Conference On Computer Design: Vlsi in Computers and Processors. 352-356.  1
1993 Velamuri R, Landsberg PJ, Zukowski CA. Multi-queue flexible buffer manager architecture Ieee Global Telecommunications Conference. 3: 1401-1405.  1
1993 Lin PS, Zukowski CA. Jitter due to signal history in digital logic circuits and its control strategies Proceedings - Ieee International Symposium On Circuits and Systems. 3: 2114-2117.  1
1993 Landsberg P, Tretz C, Zukowski C. Efficient macromodel for static CMOS multi-port memories Proceedings of the Custom Integrated Circuits Conference. 8.2.1.-8.2.4.  1
1992 Pei TB, Zukowski C. Putting routing tables in silicon Ieee Network. 6: 42-50. DOI: 10.1109/65.120723  1
1992 Pei TB, Zukowski C. High-Speed Parallel CRC Circuits in VLSI Ieee Transactions On Communications. 40: 653-657. DOI: 10.1109/26.141415  1
1991 Zukowski CA. High-Speed Data Transmission Using Low-Frequency Clocks Ieee Transactions On Circuits and Systems. 38: 273-280. DOI: 10.1109/31.101320  1
1991 Zukowski C, Pei TB. VLSI implementations of ATM buffer management Conference Record - International Conference On Communications. 2: 716-720.  1
1991 Chen DP, Zukowski C. CMOS optimization including logic family mixing Proceedings - Ieee International Symposium On Circuits and Systems. 4: 2240-2243.  1
1991 Pei TB, Zukowski C. VLSI implementation of routing tables: Tries and CAMs Proceedings - Ieee Infocom. 2: 515-524.  1
1990 Monderer B, Pacifici G, Zukowski C. The cylinder switch: An architecture for a manageable VLSI giga-cell switch Conference Record - International Conference On Communications. 2: 567-571.  1
1990 Zukowski C, Gristede G, Ruehli A. Measuring error propagation in waveform relaxation algorithms 1990 Ieee International Conference On Computer-Aided Design. Digest of Technical Papers. 170-173.  1
1988 Glasser LA, Zukowski CA. Continuous Models for Communication Density Constraints on Multiprocessor Performance Ieee Transactions On Computers. 37: 652-656. DOI: 10.1109/12.2204  1
1988 Zukowski C, Shum K. Matched-delay CMOS TDM multiplexer cell . 352-355.  1
1988 Zukowski C, Chen DP. Variable reduction in MOS timing models . 124-128.  1
1986 Zukowski CA. BOUNDING APPROACH TO VLSI CIRCUIT SIMULATION Bounding Approach to Vlsi Circuit Simul 1
1986 Zukowski CA. RELAXING BOUNDS FOR LINEAR RC MESH CIRCUITS Ieee Transactions On Computer-Aided Design of Integrated Circuits and Systems. 305-312.  1
1985 Wyatt JL, Zukowski CA, Penfield P. STEP RESPONSE BOUNDS FOR SYSTEMS DESCRIBED BY M-MATRICES, WITH APPLICATION TO TIMING ANALYSIS OF DIGITAL MOS CIRCUITS. Proceedings of the Ieee Conference On Decision and Control. 1552-1557.  1
1985 Yu Q, Wyatt JL, Zukowski C, Tan HN, O'Brien P. IMPROVED BOUNDS ON SIGNAL DELAY IN LINEAR RC MODELS FOR MOS INTERCONNECT Proceedings - Ieee International Symposium On Circuits and Systems. 903-906.  1
1985 Zukowski CA, Wyatt JL, Glasser LA. BOUNDING TECHNIQUES AND APPLICATIONS FOR VLSI CIRCUIT SIMULATION Proceedings - Ieee International Symposium On Circuits and Systems. 163-166.  1
1985 Lang JH, Zukowski CA, LaMaire RO, An C. INTEGRATED-CIRCUIT LOGARITHMIC ARITHMETIC UNITS Ieee Transactions On Computers. 475-483.  1
1984 Zukowski CA, Wyatt JL. Sensitivity of Nonlinear One-Port Resistor Networks Ieee Transactions On Circuits and Systems. 31: 1048-1051. DOI: 10.1109/TCS.1984.1085455  1
1983 Wyatt JL, Zukowski C, Glasser LA, Bassett P, Penfield P. WAVEFORM BOUNDING APPROACH TO TIMING ANALYSIS OF DIGITAL MOS IC'S . 392-395.  1
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