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Colin Weltin-Wu, Ph.D. - Publications

Affiliations: 
2012 Electrical Engineering Columbia University, New York, NY 
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11 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2015 Weltin-Wu C, Familier E, Galton I. A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs Ieee Transactions On Circuits and Systems I: Regular Papers. 62: 2013-2023. DOI: 10.1109/Tcsi.2015.2440737  0.357
2015 Weltin-Wu C, Zhao G, Galton I. A 3.5 GHz digital fractional-N PLL frequency synthesizer based on ring oscillator frequency-to-digital conversion Ieee Journal of Solid-State Circuits. 50: 2988-3002. DOI: 10.1109/Jssc.2015.2468712  0.395
2015 Weltin-Wu C, Zhao G, Galton I. A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 58: 438-439. DOI: 10.1109/ISSCC.2015.7063114  0.394
2013 Weltin-Wu C, Tsividis Y. An event-driven clockless level-crossing ADC with signal-dependent adaptive resolution Ieee Journal of Solid-State Circuits. 48: 2180-2190. DOI: 10.1109/Jssc.2013.2262738  0.771
2012 Weltin-Wu C, Tsividis Y. An event-driven, alias-free ADC with signal-dependent resolution Ieee Symposium On Vlsi Circuits, Digest of Technical Papers. 28-29. DOI: 10.1109/VLSIC.2012.6243773  0.733
2012 Kurchuk M, Weltin-Wu C, Morche D, Tsividis Y. Event-driven GHz-range continuous-time digital signal processor with activity-dependent power dissipation Ieee Journal of Solid-State Circuits. 47: 2164-2173. DOI: 10.1109/Jssc.2012.2203459  0.542
2011 Kurchuk M, Weltin-Wu C, Morche D, Tsividis Y. GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 232-233. DOI: 10.1109/ISSCC.2011.5746298  0.542
2010 Weltin-Wu C, Temporiti E, Cusmai M, Baldi D, Svelto F. Insights into wideband fractional ADPLLs: Modeling and calibration of nonlinearity induced fractional spurs Ieee Transactions On Circuits and Systems I: Regular Papers. 57: 2259-2268. DOI: 10.1109/TCSI.2010.2071650  0.474
2010 Temporiti E, Weltin-Wu C, Baldi D, Cusmai M, Svelto F. A 3.5 GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation Ieee Journal of Solid-State Circuits. 45: 2723-2736. DOI: 10.1109/JSSC.2010.2077370  0.357
2010 Weltin-Wu C, Temporiti E, Baldi D, Cusmai M, Svelto F. A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation Digest of Technical Papers - Ieee International Solid-State Circuits Conference. 53: 468-469. DOI: 10.1109/ISSCC.2010.5433846  0.333
2009 Temporiti E, Weltin-Wu C, Baldi D, Tonietto R, Svelto F. A 3 GHz fractional all-digital pLL with a 1.8 MHz bandwidth implementing spur reduction techniques Ieee Journal of Solid-State Circuits. 44: 824-834. DOI: 10.1109/Jssc.2008.2012363  0.603
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