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Hayden K. So, Ph.D. - Publications

Affiliations: 
2007 University of California, Berkeley, Berkeley, CA, United States 
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13 high-probability publications. We are testing a new system for linking publications to authors. You can help! If you notice any inaccuracies, please sign in and mark papers as correct or incorrect matches. If you identify any major omissions or other inaccuracies in the publication list, please let us know.

Year Citation  Score
2021 Wang M, Lee KCM, Chung BMF, Bogaraju SV, Ng HC, Wong JSJ, Shum HC, Tsia KK, So HK. Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network. Ieee Transactions On Neural Networks and Learning Systems. PMID 33434136 DOI: 10.1109/TNNLS.2020.3046452  0.333
2019 Shi R, Wong JSJ, So HK. High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing Journal of Imaging. 5: 34. DOI: 10.3390/Jimaging5030034  0.367
2019 Engelhardt N, So HK. GraVF-M: Graph Processing System Generation for Multi-FPGA Platforms Acm Transactions On Reconfigurable Technology and Systems. 12: 1-28. DOI: 10.1145/3357596  0.385
2019 Jaiswal MK, So HK. Design of quadruple precision multiplier architectures with SIMD single and double precision support Integration. 65: 163-174. DOI: 10.1016/J.Vlsi.2018.12.002  0.318
2018 So HK, Gross WJ. Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors Journal of Signal Processing Systems. 90: 1-2. DOI: 10.1007/S11265-017-1247-5  0.324
2018 Jaiswal MK, So HK. An Unified Architecture for Single, Double, Double-Extended, and Quadruple Precision Division Circuits Systems and Signal Processing. 37: 383-407. DOI: 10.1007/S00034-017-0559-9  0.434
2017 Engelhardt N, So HK. Towards Flexible Automatic Generation of Graph Processing Gateware Heart. 5. DOI: 10.1145/3120895.3120896  0.333
2017 Lin CY, Jiang Z, Fu C, So HK, Yang H. FPGA High-level Synthesis versus Overlay: Comparisons on Computation Kernels Acm Sigarch Computer Architecture News. 44: 92-97. DOI: 10.1145/3039902.3039919  0.407
2017 Jaiswal MK, So HK. Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division Ieee Transactions On Circuits and Systems I-Regular Papers. 64: 386-398. DOI: 10.1109/Tcsi.2016.2607227  0.417
2013 Lin CY, Wong N, So HK. Design space exploration for sparse matrix‐matrix multiplication on FPGAs International Journal of Circuit Theory and Applications. 41: 205-219. DOI: 10.1002/Cta.796  0.386
2011 Ng C, Wong N, So HK, Ng T. On IIR-based bit-stream multipliers International Journal of Circuit Theory and Applications. 39: 149-158. DOI: 10.1002/Cta.623  0.366
2010 Tsang C, So HK. Dynamic power reduction of FPGA-based reconfigurable computers using precomputation Acm Sigarch Computer Architecture News. 38: 87-92. DOI: 10.1145/1926367.1926382  0.346
2008 So HK, Brodersen R. A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH Acm Transactions On Embedded Computing Systems. 7: 1-28. DOI: 10.1145/1331331.1331338  0.499
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